Enhanced Product ADAS3022-EP
Rev. 0 | Page 11 of 21
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
15983-004
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
2. CONNECT THE EXPOSED PADDLE TO VSSH.
IN0
NC
AUX–
VDDH
VSSH
REFN
REFN
RGND
REF2
REF1
REFIN
RCAP
NC
AVDD
DVDD
ACAP
DCAP
AGND
AGND
DGND
DGND
IN1
IN2
IN3
AUX+
IN4
IN5
IN6
IN7
COM
CS
DIN
RESET
PD
VIO
SCK
SDO
BUSY
CNV
NC
1
2
3
4
5
6
7
8
9
10
23
24
25
26
27
28
29
30
22
21
11
12
13
15
17
16
18
19
20
14
33
34
35
36
37
38
39
40
32
31
ADAS3022-EP
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 to 4 IN0 to IN3 AI Input Channel 0 to Input Channel 3.
5 AUX+ AI Auxiliary Input Channel Positive Input.
6 to 9 IN4 to IN7 AI Input Channel 4 to Input Channel 7.
10 COM AI
IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The
maximum voltage on this pin is ±10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case,
the maximum voltage on this pin is ±12.228 V. AUX+ and AUX− are not referenced to COM.
11
CS
DI
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin
when sharing the serial bus. For a dedicated ADAS3022-EP serial interface, CS can be tied to DGND or
CNV to simplify the interface.
12 DIN DI
Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK
rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is
the falling edge of BUSY. The configuration register can be written to during and after a conversion.
13 RESET DI
Asynchronous Reset. A low to high transition resets the ADAS3022-EP. The current conversion, if active,
is aborted and CFG is reset to the default state.
14, 29, 30 NC N/A No Connect. This pin is not connected internally.
15 PD DI
Power-Down. A low to high transition powers down the ADAS3022-EP, minimizing the bias current.
Note that this pin must be held high until the user is ready to power on the device; after powering on
the device, the user must wait 100 ms until the reference is enabled and then wait for the completion of
two dummy conversions before the device is ready to convert.
16 SCK DI
Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022-EP are synchronized with
SCK.
17 VIO P
Digital Interface Supply. Nominally, this supply is at the same voltage as the supply of the host
interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
18 SDO DO
Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges.
The conversion result is output in twos complement format.
19 BUSY DO
Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or
writing data during the quiet conversion phase (t
QUIET
) may cause incorrect bit decisions.
20 CNV DI Convert Input. A conversion is initiated on the rising edge of this pin.
21, 22 DGND P Digital Ground. Connect these pins to the system digital ground plane.
23, 24 AGND P Analog Ground. Connect these pins to the system analog ground plane.
25 DCAP P
Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 μF
capacitor and a 0.1 μF local capacitor.
26 ACAP P
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all
of the supporting analog circuits with the exception of the internal reference. Decouple this internally
regulated output using a 10 μF capacitor and a 0.1 μF local capacitor.
