Enhanced Product ADAS3022-EP
Rev. 0 | Page 7 of 21
Parameter Test Conditions/Comments Min Typ Max Unit
1
VDDH Capacitance, I
VDDH
PGIA gain = 0.16 3.0 3.5 mA
PGIA gain = 0.2 3.0 3.5 mA
PGIA gain = 0.4 3.5 4.0 mA
PGIA gain = 0.8 5.0 5.5 mA
PGIA gain = 1.6 8.5 9.5 mA
PGIA gain = 3.2 15.5 17.5 mA
PGIA gain = 6.4 15.5 17.5 mA
All PGIA gains, PD = 1 100 μA
Current at VSSH Supply, I
VSSH
PGIA gain = 0.16 −3.0 −2.5 mA
PGIA gain = 0.2 −3.0 −2.5 mA
PGIA gain = 0.4 −3.5 −3.0 mA
PGIA gain = 0.8 −5.5 −4.5 mA
PGIA gain = 1.6 −9.5 −8.0 mA
PGIA gain = 3.2 −17.5 −15 mA
PGIA gain = 6.4 −17.5 −15 mA
All PGIA gains, PD = 1 10 μA
Current at AVDD, I
AVDD
PGIA gain = 6.4, reference buffer enabled 18 21.0 mA
All other PGIA gains, reference buffer
enabled
16 19.0 mA
PGIA gain = 6.4, reference buffer disabled 14 17.5 mA
All other PGIA gains, reference buffer
disabled
12 16.0 mA
All PGIA gains, PD = 1 100 μA
Current at DVDD, I
DVDD
All PGIA gains, PD = 0 2.5 3.5 mA
All PGIA gains, PD = 1 10 μA
Current at VIO, I
VIO
VIO = 3.3 V, PD = 0 0.30 1.2 mA
PD = 1 10 μA
Power Supply Sensitivity
At T
A
= 25°C External reference
PGIA gain = 0.16, 0.2, 0.4, and 0.8;
VDDH/VSSH ± 5%
±0.5 LSB
PGIA gain = 3.2, VDDH/VSSH ± 5% ±1.0 LSB
PGIA gain = 6.4, VDDH/VSSH ± 5% ±2.0 LSB
PGIA gain = 0.16, AVDD/DVDD ± 5% ±0.6 LSB
PGIA gain = 0.2, AVDD/DVDD ± 5% ±0.8 LSB
PGIA gain = 0.4, AVDD/DVDD ± 5% ±1.0 LSB
PGIA gain = 0.8, AVDD/DVDD ± 5% ±1.5 LSB
PGIA gain = 1.6, AVDD/DVDD ± 5% ±2.0 LSB
PGIA gain = 3.2, AVDD/DVDD ± 5% ±3.5 LSB
PGIA gain = 6.4, AVDD/DVDD ± 5% ±7.0 LSB
TEMPERATURE RANGE
Specified Performance T
MIN
to T
MAX
−55 +105 °C
1
LSB means least significant bit and changes depending on the voltage range.
2
The common-mode voltage (V
CM
) for a PGIA gain of 0.16 or 0.2 is 0 V.
3
All ac accuracy specifications expressed in decibels are referred to a full-scale range (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted.
4
This is the output from the internal band gap reference.
5
There is no pipeline delay. Conversion results are available immediately after a conversion is complete.
6
The differential input common-mode voltage (V
CM
) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and
VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤
INx/COM ≤ (VDDH − 2.5 V).
ADAS3022-EP Enhanced Product
Rev. 0 | Page 8 of 21
TIMING SPECIFICATIONS
VDDH = 15 V ± 5%, VSSH = −15 V ± 5%, AVDD = DVDD = 5 V ± 5%, VIO = 1.8 V to AVDD, internal reference, V
REF
= 4.096 V,
f
S
= 1 MSPS unless otherwise noted. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter Symbol Min Typ Max Unit
Time Between Conversions t
CYC
Warp Mode,
1
CMS = 0 1 1000 µs
Normal Mode (Default), CMS = 1 1.1 µs
Conversion Time: CNV Rising Edge to Data Available t
CONV
Warp Mode, CMS = 0
825
ns
Normal Mode (Default), CMS = 1 925 1000 ns
Auxiliary ADC Input Channel Acquisition Time t
ACQ
600 ns
CNV Pulse Width t
CH
10 ns
CNV High to Hold Time (Aperture Delay) t
AD
2 ns
CNV High to Busy Delay t
CBD
520 ns
Safe Data Access Time During Conversion t
DDC
500 ns
Quiet Conversion Time (BUSY High) t
QUIET
Warp Mode, CMS = 0 400 ns
Normal Mode (Default), CMS = 1 500 ns
Data Access During Quiet Conversion Time t
DDCA
Warp Mode, CMS = 0 200 ns
Normal Mode (Default), CMS = 1 300 ns
SCK Period t
SCK
15 ns
SCK Low Time t
SCKL
5 ns
SCK High Time t
SCKH
5 ns
SCK Falling Edge to Data Valid t
SDOH
4 ns
SCK Falling Edge to Data Valid Delay
t
SDOD
VIO > 4.5 V 12 ns
VIO > 3.0 V 18 ns
VIO > 2.7 V 24 ns
VIO > 2.3 V 25 ns
VIO > 1.8 V 37 ns
CS
/RESET/PD Low to SDO t
EN
VIO > 4.5 V 15 ns
VIO > 3.0 V 16 ns
VIO > 2.7 V 18 ns
VIO > 2.3 V 23 ns
VIO > 1.8 V
28
ns
CS
/RESET/PD High to SDO High Impedance t
DIS
25 ns
DIN Valid Setup Time from SCK Rising Edge t
DINS
4 ns
DIN Valid Hold Time from SCK Rising Edge t
DINH
4 ns
CNV Rising to
CS
t
CCS
5 ns
RESET/PD High Pulse t
RH
5 ns
1
Exceeding the maximum time has an effect on the accuracy of the conversion.
Enhanced Product ADAS3022-EP
Rev. 0 | Page 9 of 21
Timing Diagrams
I
OL
500µA
500µA
I
OH
1.4V
T
O SDO
C
L
50pF
15983-002
Figure 2. Load Circuit for Digital Interface Timing
3
0% VI
O
70% VIO
2V OR VIO – 0.5V
1
0.8V OR 0.5V
2
0.8V OR 0.5V
2
2V OR VIO – 0.5V
1
t
DELAY
t
DELAY
1
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
2
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
15983-003
Figure 3. Voltage Levels for Timing
ACQUISITION (n)
UNDEFINED
PHASE
POWER
UP
CONVERSION (n – 1)
UNDEFINED
CNV
BUSY
DIN
CS
SDO
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (
t
DDC
), AFTER A CONVERSION (
t
DAC
), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO
t
DDCA
WHILE BUSY IS ACTIVE (SEE THE ADAS3022 DATA SHEET FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (
t
AD
) SHOULD ELAPSE PRIOR TO DATA ACCESS.
DATA
INVALID
SCK
1 1
1
16/32
1616
X 16
NOTE 3
NOTE 1
NOTE 2
NOTE 2
NOTE 1
NOTE 4
NOTE 5
CFG
INVALID
CFG (n + 2)
DATA (n – 1)
INVALID
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n)
UNDEFINED
DATA (n – 1)
INVALID
CFG (n + 2)
CFG (n + 3)
DATA (n)
INVALID
ACQUISITION
(n + 2)
CONVERSION (n + 1)
UNDEFINED
DATA (n)
INVALID
CFG (n + 3)
CFG (n + 4)
DATA (n + 1)
INVALID
ACQUISITION
(n + 3)
PHASE
CONVERSION
(n + 2)
CNV
BUSY
DIN
CS
SDO
DATA (n + 1)
INVALID
SCK
1
1
CFG (n + 4) CFG (n + 5)
DATA (n + 2)
ACQUISITION
(n + 4)
CONVERSION
(n + 3)
DATA (n + 2)
CFG (n + 5)
CFG (n + 6)
DATA (n + 3)
CONVERSION
(n + 4)
DATA (n + 3)
CFG (n + 6)
EOC
EOC EOC EOC
EOC SOC
SOC
t
DDC
t
CYC
t
QUIET
t
DAC
t
ACQ
t
AD
t
DDCA
15983-028
Figure 4. General Timing Diagram

ADAS3022SCPZ-EP-RL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Biopolar 1MSPS 16 bit DAS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet