CY2DP818ZC

CY2DP818
1:8 Clock Fanout Buffer
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-07061 Rev. *B Revised August 5, 2009
Features
Low-voltage operation V
DD
= 3.3V
1:8 fanout
Operation to 350 MHz
Single input configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50 ohm load
Low input capacitance
Low output skew
Low propagation delay (tpd = 4 ns, typical)
Commercial and Industrial temperature ranges
38-Pin TSSOP Package
Description
The Cypress CY2DP818 fanout buffer features a single LVDS or
a single ended LVTTL compatible input and eight LVPECL output
pairs.
Designed for data-communications clock management
applications, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from single
ended to LVPECL and/or for the distribution of LVPECL based
clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the InConfig pin for single ended or
differential input.
Logic Block Diagram
INPUT
(LVPECL / LVDS / LVTTL)
OUTPUT
(LVPECL)
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
INPUT A
INPUT B
InConfig
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CY2DP818
Document #: 38-07061 Rev. *B Page 2 of 7
Pinouts
Pin Configuration
Figure 1. 38-Pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
VDD
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4B
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q4A
GND
VDD
GND
GND
VDD
InConfig
INPUT A
INPUT B
GND
GND
CY2DP818
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
Pin Description
Pin Number Pin Name Type Description
1, 9, 12, 18, 19, 20, 38 GND POWER Ground
2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD POWER Power Supply
10, 11 Input A, Input B Default: LVPECL/LDVS
Optional: LVTTL/LVCMOS
single pin
Clock Input. Either differential
LVPECL/LVDS or single-ended
LVTTL/LVCMOS, as determined by
InConfig. See Table 1 and Table 2 for
details.
37, 36, 35, 34,
33, 32, 31, 30,
28, 27, 26, 25,
24, 23, 22, 21
Q1(A,B), Q2(A,B)
Q3(A,B), Q4(A,B)
Q5(A,B), Q6(A,B)
Q7(A,B), Q8(A,B)
LVPECL Differential Output Clocks
7 InConfig LVTTL/LVCMOS Control Input. Selects input type: either
differential LVPECL/LVDS or
single-ended LVTTL/LVCMOS
See Table 1 and Table 2 for details.
Table 1. Input Receiver Configuration for Differential or LVTTL/LVCMOS
InConfig (Pin 7) Input Receiver Family Input Receiver Type
1 LVTTL or LVCMOS Single ended, non-inverting or inverting, void of bias resistors
0 LVDS or LVPECL Differential, void of internal termination
Table 2. Single ended LVTTL/LVCMOS Input Logic (InConfig = 1)
Input A (+) Pin 10 Input B (–) Pin 11 Output Clock QnA Pins
Input Ground True
Input VDD Invert
Ground Input Invert
VDD Input True
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CY2DP818
Document #: 38-07061 Rev. *B Page 3 of 7
Maximum Ratings
[1]
Storage Temperature:................................ –65°C to + 150°C
Ambient Temperature: .................................. –40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and V
DD
only) .......................................–0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only)........................................–0.3V to V
DD
+ 0.3V
DC Input Voltage ...................................–0.3V to V
DD
+ 0.3V
DC Output Voltage.................................–0.3V to V
DD
+ 0.9V
Power Dissipation....................................................... 0.75W.
DC Electrical Specifications
Table 3. Power Supply Characteristics
Parameter Description Test Conditions Min Typ Max Unit
ICC Dynamic Power Supply Current V
DD
= Max
Input toggling 50% Duty Cycle,
Outputs Open
1.5 2.0 mA/
MHz
IC Total Power Supply Current V
DD
= Max
Input toggling 50% Duty Cycle,
Outputs 50 ohms
fL=100 MHz
350 mA
IC Core Core current when output loads are
disabled
V
DD
= Max
Input toggling 50% Duty Cycle,
Outputs not connected to VTT
fL=100 MHz
50 mA
Table 4. LVDS Input, V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
V
ID
Magnitude of Differential Input Voltage 100 600 mV
V
IC
Common-mode of Differential Input
VoltageIV
ID
I (min and max)
IVIDI/2 2.4–(IVIDI/2) V
V
IH
Input High Voltage Guaranteed Logic High Level 2 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 0.8 V
I
IH
Input High Current V
DD
= Max, V
IN
= V
DD
±10 ±20 μA
I
IL
Input Low Current V
DD
= Max, V
IN
= V
SS
±10 ±20 μA
Table 5. LVPECL Input, V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
V
ID
Differential Input Voltage p-p Guaranteed Logic High Level 400 2600 mV
V
IH
Input High Voltage Guaranteed Logic High Level 2.15 2.4 V
V
IL
Input Low Voltage Guaranteed Logic Low Level 1.5 1.8 V
I
IH
Input High Current V
DD
= Max, V
IN
= V
DD
±10 ±20 μA
I
IL
Input Low Current V
DD
= Max, V
IN
= V
SS
±10 ±20 μA
V
CM
Common-mode Voltage 225 mV
Table 6. LVTTL/LVCMOS Input, V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
V
IH
Input High Voltage 2 V
V
IL
Input Low Voltage 0.8 V
I
IH
Input High Current V
DD
= Max, V
IN
= 2.7V 1 μA
I
IL
Input Low Current V
DD
= Max, V
IN
= 0.5V –1 μA
Note
1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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CY2DP818ZC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:8 350MHZ 38TSSOP
Lifecycle:
New from this manufacturer.
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