CY2DP818ZC

CY2DP818
Document #: 38-07061 Rev. *B Page 4 of 7
AC Switching Characteristics
I
I
Input High Current V
DD
= Max, V
IN
= V
DD
(Max) 20 μA
V
IK
Clamp Diode Voltage V
DD
= Min, I
IN
= –18mA –0.7 –1.2 V
V
H
Input Hysteresis 80 mV
Table 7. LVPECL Output, V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
V
OD
Driver Differential Output
voltage p-p
V
DD
= Min, V
IN
= V
IH
or V
IL
, R
L
= 50 Ω 1000 3600 mV
V
OC
Driver common-mode p-p V
DD
= Min, V
IN
= V
IH
or V
IL
, R
L
= 50 Ω 300 mV
t
R
Rise Time Differential 20% to 80%, C
L
= 10 pF to GND,
R
L
= 50 Ω to GND
300 1200 ps
t
F
Fall Time
V
OH
Output High Voltage V
DD
= Min, V
IN
= V
IH
or V
IL
, I
OH
= –12 mA 2.1 3.0 V
V
OL
[2]
Output Low Voltage V
DD
= Min, V
IN
= V
IH
or V
IL
0.8 1.3 V
I
OS
Short Circuit Current V
DD
= Max, V
OUT
= GND –125 –150 mA
Table 8. V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
t
PLH
Propagation Delay – Low to High V
ID
= 100 mV 3 4 5 ns
t
PHL
Propagation Delay – High to Low V
ID
= 100 mV 3 4 5 ns
t
SK(0)
Output Skew: Skew between outputs of the same package (in phase) 0.2 ns
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
–t
PLH
)
0.2 ns
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type. Same
input signal level and output load.
V
ID
= 100 mV 1 ns
Table 6. LVTTL/LVCMOS Input, V
DD
= 3.3V ±5%, T
A
= 0°C to 70°C or –40°C to 85°C
Parameter Description Conditions Min Typ Max Unit
Note
2. V
OL
levels are dependent on the termination voltage V
TT
and termination resistance R
TT
. Changing either of these values will affect V
OL
.
Table 9. High frequency Parametrics
Parameter Description Conditions Min Typ Max Unit
Fmax
Maximum frequency
V
DD
= 3.3V
45%–55% duty cycle
Standard load circuit
350 MHz
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CY2DP818
Document #: 38-07061 Rev. *B Page 5 of 7
Figure 2. Driver Design
Figure 3. Standard Termination
Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time
[3,4,5,6]
Figure 5. Test Circuit and Voltage Definitions for the Driver Common Mode Output Voltage
[3,4,5,6]
80%
20%
0V Differential
QnA - QnB
t
F
1.4 V
1.0 V
INPUT A
INPUT B
QnA
QnB
t
R
t
PLH
t
PHL
Notes
3. All input pulses are supplied by a frequency generator with the following characteristics: t
R
and t
F
1 ns; pulse rerate = 50 Mpps; pulse width = 10 ± 0.2 ns.
4. RL = 50 ohm ± 1%; Zline = 50 ohm 6”.
5. CL includes instrumentation and fixture capacitance within 6 mm of the UT.
6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to V
DD
– 2V.
2.0V
1.6V
INPUT A
INPUT B
Next Device
VODVOC
TPA
TPC
TPB
50
50
GND
150
150
Standard Termination
Pulse
Generator
A
B
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CY2DP818
Document #: 38-07061 Rev. *B Page 6 of 7
Package Drawing and Dimensions
Figure 6. 38-Pin TSSOP (4.40 mm Body) Z38 and ZZ38
Ordering Information
Part Number Package Type Product Flow
CY2DP818ZI 38-pin TSSOP Industrial, –40° to 85°C
CY2DP818ZIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZC 38-pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
Pb-Free
CY2DP818ZXI 38-pin TSSOP Industrial, –40° to 85°C
CY2DP818ZXIT 38-pin TSSOP–Tape and Reel Industrial, –40° to 85°C
CY2DP818ZXC 38-pin TSSOP Commercial, 0°C to 70°C
CY2DP818ZXCT 38-pin TSSOP–Tape and Reel Commercial, 0°C to 70°C
51-85151-*A
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CY2DP818ZC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFFER 1:8 350MHZ 38TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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