LTC4558EUD#PBF

LTC4558
7
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BLOCK DIAGRAM
7
4
I/OA
V
CCA
1
V
CCB
18
I/OB
19
RSTB
20
17161121
CLKB
6
RSTA
5
CLKA
14
CLKRUNA
8
DATA
9
RSTIN
10
CLKIN
LDOA LDOB
V
BATT
DV
CC
DV
CC
3
DV
CC
2
CONTROL
LOGIC
4558 BD
12
VSELA ENABLEA VSELB ENABLEB
13
CSELGND
15
CLKRUNB
LTC4558
8
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OPERATION
The LTC4558 features two independent SIM/Smart Card
channels. Only one of these channels may be open for
communication at a time however both channels can be
enabled and made ready for communication using the
ENABLEA and ENABLEB pins. This allows faster transi-
tion from one channel to the other. Each channel is able
to produce two voltage levels, 1.8V and 3V. The channel
selection and voltage selection are controlled by the CSEL,
VSELA and VSELB pins as shown in the table below:
Bidirectional Channels
The bidirectional channels are level shifted to the appro-
priate V
CCA,B
voltages at the I/OA,B pins. An NMOS pass
transistor performs the level shifting. The gate of the NMOS
transistor is biased such that the transistor is completely
off when both sides have relinquished the channel. If one
side of the channel asserts a LOW, then the transistor will
convey the LOW to the other side. Note that current passes
from the receiving side of the channel to the transmitting
side. The low output voltage of the receiving side will be
dependent upon the voltage at the transmitting side plus
the IR drop of the pass transistor.
When a card socket is selected, it becomes a candidate
to drive data on the DATA pin and likewise receive data
from the DATA pin. When a card socket is deselected, its
I/O pin will be pulled HIGH and communication with the
DATA pin will be disabled. If both channels are disabled,
a weak pull-up ensures that the DATA pin is held HIGH,
as long as DV
CC
is powered.
Dynamic Pull-Up Current Sources
The current sources on the bidirectional pins (DATA,I/OA,B)
are dynamically activated to achieve a fast rise time with
a relatively small static current. Once a bidirectional pin
is relinquished, a small start-up current begins to charge
the node. An edge rate detector determines if the pin is
released by comparing its slew rate with an internal refer-
ence value. If a valid transition is detected, a large pull-up
current enhances the edge rate on the node. The higher
slew rate corroborates the decision to charge the node
thereby affecting a dynamic form of hysteresis.
Reset Channels
When a card is selected, the reset channel provides a level
shifted path from the RSTIN pin to the RST pin of the
selected card. When a card is deselected, the last state of
the RSTA,B pin is latched. This allows a deselected card to
remain active, and therefore eliminates delays associated
with card initialization.
Clock Run Mode
Various SIM/Smart Cards may have different requirements
for the state of the clock pin when the channel is not open
for communication. The CLKRUNA,B pins allow the user to
select whether the clock is brought LOW after the channel
is deselected or allowed to run. If a channel is enabled,
bringing its CLKRUN pin HIGH will transmit the clock to
the corresponding card socket, whether or not the channel
is selected using the CSEL.
Figure 1. Dynamic Pull-Up Current Source
Table 1. Channel and Voltage Truth Table
CSEL VSELA VSELB
SELECTED
CARD
VOLTAGES
A B
0 0 0 A 1.8V 1.8V
0 0 1 A 1.8V 3V
0 1 0 A 3V 1.8V
011 A 3V3V
1 0 0 B 1.8V 1.8V
1 0 1 B 1.8V 3V
1 1 0 B 3V 1.8V
111 B 3V3V
V
REF
4558 F01
I
START
BIDIRECTIONAL
PIN
LOCAL
SUPPLY
dv
dt
+
LTC4558
9
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Activation/Deactivation
Activation and deactivation sequencing is handled by built-
in circuitry. Each channel may be activated or deactivated
independently of the other. The activation sequence for
each channel is initiated by bringing the ENABLEA,B pin
HIGH. The activation sequence is outlined below:
1. The RSTA,B, CLKA,B and I/OA,B pins are held LOW.
2. V
CCA,B
is enabled.
3. After V
CCA,B
is stable at its selected level, the I/OA,B
and RSTA,B channels are enabled.
4. The clock channel is enabled on the rising edge of the
second clock cycle after the I/OA,B pin is enabled.
The deactivation sequence is initiated by bringing the
ENABLEA,B pin LOW. The deactivation sequence is out-
lined below:
1. The reset channel is disabled and RSTA,B is brought
LOW.
2. The clock channel is disabled and the CLKA,B pin is
brought LOW two clock cycles after ENABLEA,B is
brought LOW. If the clock is not running, the clock
channel will be disabled approximately 9μs after the
ENABLEA,B pin is brought LOW.
3. The I/O channel is disabled and the I/OA,B pin is brought
LOW approximately 9μs after the ENABLEA,B pin is
brought LOW.
4. V
CCA,B
will be depowered after the I/OA,B pin is brought
LOW.
The activation or deactivation sequences will take place
every time a card channel is enabled or disabled. When
a channel is deselected using the CSEL pin, the RSTA,B
state is latched, the I/OA,B channel becomes high imped-
ance and CLKA,B is brought LOW after a maximum of two
clock cycles.
Fault Detection
The V
CCA,B
, I/OA,B, RSTA,B, CLKA,B and DATA pins are all
protected against short-circuit faults. While there are no
logic outputs to indicate that a fault has occurred, these
pins will be able to tolerate the fault condition until it has
been removed.
The V
CCA,B
, I/OA,B, and RSTA,B pins possess fault protec-
tion circuitry which will limit the current available to the
pins. Each V
CC
pin is capable of supplying approximately
90mA (typ) before the output voltage is reduced.
The CLKA,B pins are designed to tolerate faults by reducing
the current drive capability of their output stages. After a
fault is detected by the internal fault detection logic, the
logic waits for a fault detection delay to elapse before
reducing the current drive capability of the output stage.
The reduced current drive allows the LTC4558 to detect
when the fault has been removed.
OPERATION

LTC4558EUD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Power Management Specialized - PMIC 2x SIM/Smart Card Pwr S & Int
Lifecycle:
New from this manufacturer.
Delivery:
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