LT3507A
19
3507afa
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voltage is substantially higher than 0.8V at steady state and
effectively turns off D1. D2 and D3 will therefore conduct
the same current and offer tight matching between V
FB2
and the internal precision 0.8V reference. In the ratiometric
mode with R6 = R2, TRK/SS2 equals 0.8V at steady state.
D1 will divert part of the bias current and make V
FB2
slightly
lower than 0.8V. Although this error is minimized by the
exponential I-V characteristic of the diodes, it does impose
a finite amount of output voltage deviation. Further, when
channel 1s output experiences dynamic excursions (under
load transient, for example), channel 2 will be affected as
well. Setting R6 to a value that pushes the TRK/SS2 voltage
to 1V at steady state will eliminate these problems while
providing near ratiometric tracking.
The example shows channel 2 tracking channel 1, however
any channel may be set up to track any other channel.
If a capacitor is tied from the TRK/SS pin to ground, then
the internal pull-up current will generate a voltage ramp on
this pin. This results in a ramp at the output, limiting the
inductor current and therefore input current during start-up.
A good value for the soft-start capacitor is C
OUT
/10,000,
where C
OUT
is the value of the output capacitor.
MULTIPLE INPUT SUPPLIES
V
IN1
, V
IN2
and V
IN3
are independent and can be powered
with different voltages provided V
IN1
is present when V
IN2
or V
IN3
is present. Each supply must be bypassed as close
to the V
IN
pins as possible.
For applications requiring large inductors due to high V
IN
to V
OUT
ratios, a 2-stage step-down approach may reduce
inductor size by allowing an increase in frequency. A dual
step-down application steps down the input voltage (V
IN1
)
to the highest output voltage, then uses that voltage to
power the other outputs (V
IN2
and V
IN3
). V
OUT1
must be
able to provide enough current for its output plus the
input current at V
IN2
and V
IN3
when V
OUT2
and V
OUT3
are
at maximum load. The Typical Applications section shows
a 36V to 15V, 1.8V and 1.2V 2-stage converter using this
approach.
For applications with multiple voltages, the LT3507A can
accommodate input voltages as low as 3V on V
IN2
and
applications inForMation
V
IN3
. This can be useful in applications regulating outputs
from a PCI Express bus, where the 12V input is power
limited and the 3.3V input has power available to drive
other outputs. In this case, tie the 12V input to V
IN1
and
the 3.3V input to V
IN2
and V
IN3
.
LOW DROPOUT REGULATOR
The low dropout regulator comprises an error amp, loop
compensation and a base drive amp. It uses the same 0.8V
reference as the switching regulators. It requires an external
NPN pass transistor and 2.2µF of output capacitance for
stability. The internal compensation is stable with loads
up to 300mA.
The dropout characteristics will be determined by the pass
transistor. The collector-emitter saturation characteristics
will limit the dropout voltage. Table 5 lists some suitable
NPN transistors with their saturation specifications.
The base drive voltage has a maximum voltage of 5V.
This will limit the maximum output of the regulator to
5V – V
BESAT
where V
BESAT
is the base-emitter saturation
voltage of the pass transistor.
Table 5. Low V
CESAT
Transistors
PART NUMBER
V
CESAT
AT
I
C
= 1A OUTLINE MANUFACTURER
ZXTN25012EZ 0.06 SOT89 Zetex
www.diodes.com
ZXT
N25020DG
0.075 SOT223
NSS20201JT1G 0.22 SC-89 On Semiconductor
www.onsemi.com
NSS12201L
T1G 0.08 SOT-23
CTLT3410-M621 0.28 1mm × 2mm
TLM621
Central Semiconductor
www.central-semi.com
The LDO is always on when any of the switcher channels
is on. The LDO may be shut down if it is unused by pull-
ing the FB4 pin up with a 30µA current source. The FB4
pin will clamp at about
1.25V
and the LDO will shut off
reducing power consumption. This pull-up can be sourced
from one of the LT3507A outputs provided that channel
is always on when the other channels are on.
The output stage of the LDO will drive the NPN base from
the BIAS voltage if it is at least 0.8V above the LDO DRIVE
voltage.
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applications inForMation
FB Resistor Network
The output voltage of the LDO regulator is programmed
with a resistor divider (Refer to Block Diagram) between the
emitter of the external NPN pass resistor and the feedback
pin, FB4. Choose the resistors according to
R1=R2
V
OUT4
800mV
1
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
PROGRAMMABLE OVERVOLTAGE AND
UNDERVOLTAGE LOCKOUT
The LT3507A provides two input pins that allow user-
programmable overvoltage and undervoltage lockout. Both
the trip levels and hysteresis can be set by resistor values.
V
INSW
provides a switched V
IN1
to minimize power con-
sumption in shutdown. V
INSW
is connected to V
IN1
when
the LT3507A is operating, with a saturation voltage of
about 0.3V. It is high impedance when the LT3507A is in
shutdown (all three RUN pins low).
The programmable lockout is a pair of comparators with
the trip level set at 1.2V. The OVLO comparator trips when
the OVLO pin exceeds 1.2V while the UVLO compara
-
tor trips when the UVLO pin drops below 1.2V. These
comparators shut down all four regulators until the input
voltage recovers.
The comparators also activate current sources that gener
-
ate hysteresis to eliminate chatter
. The UVLO comparator
activates a 10µA
current sink on the UVLO pin. The OVLO
comparator activates a 10µA current source on the OVLO
pin. These currents generate hysteresis voltage through
the resistance of the divider string.
Figure 11 shows a typical connection. The threshold
voltages are:
V
OVTH
=0.3V+1.2V 1+
R3
R4
V
UVTH
=0.3V+1.2V 1+
R1
R2
where 0.3V is the typical V
IN1
-V
INSW
voltage drop.
The hysteresis voltages are:
V
OVHYST
= 10µA R3
V
UVHYST
= 10µA R1
If the overvoltage lockout is not used, the OVLO pin must
be tied to ground. If the undervoltage lockout is not used,
the UVLO pin must be tied to V
INSW
.
Figure 11. Undervoltage and Overvoltage Lockout Circuit
+
+
1.2V
UVLO
UVLO
V
INSW
R3
R4
R1
R2
OVLO
10µA
10µA
OVLO
3507A F11
PCB LAYOUT
For proper operation and minimum EMI, care must be
taken during printed circuit board (PCB) layout. Figure 12
shows the high current paths in the step-down regula-
tor circuit. Note that in the step-down regulators large,
switched currents flow in the power switch, the catch
diode and the input capacitor. The loop formed by these
components should be as small as possible. Place these
components, along with the inductor and output capacitor
,
on the same side of the circuit board and connect them
on that layer. Place a local, unbroken ground plane below
these components and tie this ground plane to system
ground at one location, ideally at the ground terminal of the
output capacitor C2. Additionally, keep the SW and BOOST
nodes as small as possible and away from any FB or V
C
pins. Figure 13 shows an example of proper PCB layout.
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Figure 12. Subtracting the Current When the Switch Is On (12a) from the Current When the Switch Is Off (12b)
Reveals the Path of the High Frequency Switching Current (12c)
applications inForMation
Figure 13. Power Path Components and Topside Layout
V
IN
SW
I
OUT
– I
IN
I
IN
I
IN
I
IN
I
OUT
I
OUT
I
OUT
I
IN
GND
(12a Switch On)
V
IN
V
SW
C1 D1 C2
3507A F12
L1
SW
GND
(12c High Frequency Switching Loop)
V
IN
SW
GND
(12b Switch Off)
I
C1
THERMAL CONSIDERATIONS
The high output current capability of the LT3507A will
require careful attention to power dissipation of all the
components to insure a safe thermal design. The PCB
must provide heat sinking to keep the LT3507A cool.
The exposed pad on the bottom of the package must be
soldered to a ground plane. This ground should be tied
to other copper layers below with thermal vias; these lay
-
ers will spread the heat dissipated by the LT3507A. Place
additional vias near the catch diodes. Adding more copper
to the top and bottom layers and tying this copper to the
internal planes with vias can reduce thermal resistance
further. With these steps, the thermal resistance from die
(or junction) to ambient can be reduced to θ
JA
= 34°C/W
or less (QFN). With 100 LFPM airflow, this resistance can
fall by another 25%. Further increases in airflow will lead
to lower thermal resistance.

LT3507AIFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 3x Mono Buck Reg w/ LDO
Lifecycle:
New from this manufacturer.
Delivery:
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