LT3507A
9
3507afa
For more information www.linear.com/LT3507A
operation
The LT3507A contains three independent, constant fre-
quency, current mode, switching regulators with internal
power switches plus a low dropout linear regulator. The
three regulators share common cir
cuitry including input
source, voltage reference and oscillator, but are otherwise
independent. Operation can be best understood by refer
-
ring to the Block Diagram (Figure 1).
If the RUN pins are tied to ground, the
LT3507
A is shut
down and draws <1µA from the input source tied to V
IN1
. If
any of the RUN pins are driven above 1V, the internal bias
circuits turn on, including the internal regulator, reference,
and master oscillator. Each switching regulator will only
begin to operate when its corresponding RUN pin reaches
>1.25V. The master oscillator generates three clock signals,
with the signal for channel 1 out of phase by 180°.
The three switchers are current mode regulators. Instead
of directly modulating the duty cycle of the power switch,
the feedback loop controls the peak current in the switch
during each cycle. Compared to voltage mode control, cur
-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram shows only one of the three step-down
switching regulators. A pulse from the slave oscillator
sets
the
RS flip-flop and turns on the internal NPN bipo
-
lar power switch. Current in the switch and the external
inductor begins to increase. When this current exceeds a
level determined by the voltage at V
C
, current comparator
C1 resets the flip-flop, turning off the switch. The current
in the inductor flows through the external Schottky diode
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way, the voltage on the V
C
pin controls the current through the inductor to the output.
The internal error amplifier regulates the output voltage
by continually adjusting the V
C
pin voltage. The threshold
for switching on the V
C
pin is >0.9V and an active clamp
of 1.8V limits the output current.
Each switcher contains an extra, independent oscillator to
perform frequency foldback during overload conditions.
This slave oscillator is normally synchronized to the master
oscillator. A comparator senses when V
FB
is less than 50%
of its regulated value and switches the regulator from the
master oscillator to a slower slave oscillator. V
FB
is less than
50% of its regulated value during start-up, short-circuit
and overload conditions. Frequency foldback helps limit
switch current under these conditions.
The TRK/SS pins override the 0.8V reference for the FB
pins when the TRK/SS pins are below 0.8V. This allows
either coincident or ratiometric supply tracking on start-up
as well as a soft-start capability.
The switch drivers operate either from V
IN
or from the
BOOST pin. An external capacitor and diode are used to
generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to saturate the
internal bipolar NPN power switch for efficient operation.
The BIAS pin allows the internal circuitry to draw its current
from a lower voltage supply than the input, also reducing
power dissipation and increasing efficiency. If the voltage
on the BIAS pin falls below 3V, then its quiescent current
will flow from V
IN
.
A power good comparator trips when the FB pin is at 90% of
its regulated value. The PGOOD output is an open-collector
transistor that is off when the output is in regulation, al
-
lowing an external resistor to pull the PGOOD pin high.
Power good is valid when the LT3507
A is enabled and V
IN
is within normal operating range.
The LDO regulator uses an external NPN pass transistor to
form a linear regulator. The loop is internally compensated
to be stable with a load capacitance of 2.2µF or greater.
The LDO is disabled when all three of the RUN pins are low.
The overvoltage and undervoltage detection shuts down
the LT3507A if the OVLO pin>1.2V or the UVLO pin<1.2V.
Input overvoltage and undervoltage values are set by re
-
sistor dividers to V
INSW
. Hysteresis is provided by 10µA
currents activated when either pin trips. The hysteresis
voltage at V
IN
is the top resistor times 10µA.
