LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
13 Rev A 6/30/15
853S111AI DATA SHEET
Schematic Example
This application note provides a general design guide using
853S111AI LVPECL buffer. Figure 5 shows a schematic example of
the 853S111AI LVPECL clock buffer. In this example, the input is
driven by an LVPECL driver. CLK_SEL is set at logic high to select
PCLK0/nPCLK0 input.
Figure 5. 853S111AI Example LVPECL Clock Output Buffer Schematic
C4
0.1uF
C6 (Option)
0.1u
Zo = 50
R7
50
Zo = 50
R2
50
VCC
R1
50
VCC
VCC=3.3V
C7 (Option)
0.1u
R3
50
(U1-16)
U1
ICS853111
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
VCC
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VEE
VCCO
nQ9
Q9
nQ8
Q8
nQ7
Q7
VCCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
R4
1K
Zo = 50
C2
0.1uF
(U1-9)
R8
50
Zo = 50 Ohm
C8 (Option)
0.1u
+
-
C5
0.1uF
R10
50
R11
50
3.3V LVPECL
+
-
VCC
(U1-32)
R13
50
C1
0.1uF
Zo = 50 Ohm
R9
50
C3
0.1uF
(U1-25)
VCC
Zo = 50
(U1-1)
Rev A 6/30/15 14 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
853S111AI DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 853S111AI.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 853S111AI is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 74mA = 256.41mW
Power (outputs)
MAX
= 32.59mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 32.59mW = 325.90mW
Total Power_
MAX
(3.8V, with all outputs switching) = 256.41mW + 325.90mW = 582.31mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming a moderate air
flow of 2.5 meter per second and a multi-layer board, the appropriate value is 67.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.582W * 67.7°C/W = 124.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 32 Lead LQFP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 80.9°C/W 71.4°C/W 67.7°C/W
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
15 Rev A 6/30/15
853S111AI DATA SHEET
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
V
CCO
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.85V
(V
CCO_MAX
– V
OH_MAX
) = 0.85V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX –
1.59V
(V
CCO_MAX
– V
OL_MAX
) = 1.59V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (
VCCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO_MAX
– V
OH_MAX
))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V – 0.85V)/50] * 0.85V = 19.55mW
Pd_L = [(V
OL_MAX
(V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V – (V
CCO_MAX
– V
OL_MAX
))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.59V)/50] * 1.59V = 13.04mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.59mW
V
OUT
V
CCO
V
CCO
- 2V
Q1
RL
50Ω

853S111AYILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-10 LVPECL/ECL Fanout
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet