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853S111AYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
7 Rev A 6/30/15
853S111AI DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot and
is most often the specified plot in many applications. Phase noise is
defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "Rhode & Schwartz SMA 100A Signal
Generator 9kHz – 6GHz as external input to a Hewlett Packard 8133A
3GHz Pulse Generator".
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.07ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
Rev A 6/30/15 8 LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
853S111AI DATA SHEET
Parameter Measurement Information
LVPECL Output Load AC Test Circuit
Part-to-Part Skew
Output Rise/Fall Time
Differential Input Level
Output Skew
Propagation Delay
SCOPE
Qx
nQx
V
EE
tsk(pp)
Part 1
Part 2
V
CMR
Cross Points
V
PP
t
PD
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT
BUFFER
9 Rev A 6/30/15
853S111AI DATA SHEET
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 1 shows how a differential input can be wired to accept single
ended levels. The reference voltage V
REF
= V
CC
/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the V
REF
in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and V
CC
= 3.3V,
R1 and R2 value should be adjusted to set V
REF
at 1.25V. The values
below are for when both the single ended swing and V
CC
are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50 applications, R3 and R4 can be 100.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL
cannot be less
than -0.3V and V
IH
cannot be more than V
CC
+ 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

853S111AYILF

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Buy 853S111AYILF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution Low Skew,1-to-10 LVPECL/ECL Fanout
Lifecycle:
New from this manufacturer.
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