Datasheet
10/13
BD52xx series BD53xx series
TSZ02201-0R7R0G300040-1-2
© 2012 ROHM Co., Ltd. All rights reserved.
18.Dec.2012 Rev.005
www.rohm.com
TSZ22111・15・001
●Application Information
Explanation of Operation
For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as
threshold voltages. When the voltage applied to the V
DD
pins reaches the applicable threshold voltage, the V
OUT
terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Please refer to the Timing Waveform and Electrical
Characteristics for information on hysteresis. Because the BD52xx series uses an open drain output type, it is necessary to
connect a pull-up resistor to V
DD
or another power supply if needed [The output “High” voltage (V
OUT
) in this case becomes
V
DD
or the voltage of the other power supply].
Fig.15 (BD52xxType Internal Block Diagram) Fig.16 (BD53xxType Internal Block Diagram)
Setting of Detector Delay Time
It is possible to set the delay time at the rise of VDD using a capacitor connected to the Ct terminal.
Delay time at the rise of V
DD
t
PLH
：Time until when Vout rise to 1/2 of V
DD
after V
DD
rise up and beyond the release
voltage(V
DET
+V
DET
)
t
PLH
= -C
CT
×R
CT
×ln
C
CT
: C
T
pin External Capacitance
R
CT
: C
T
pin Internal Impedance（Please refer to Electrical Characteristics.）
V
CTH
: C
T
pin Threshold Voltage（Please refer to Electrical Characteristics.）
ln : Natural Logarithm
Reference Data of Falling Time (t
PHL
) Output
Examples of Falling Time (t
PHL
) Output
Part Number t
PHL
[µs] -40°C t
PHL
[µs] ,+25°C t
PHL
[µs],+105°C
BD5227 30.8 30 28.8
BD5327 26.8 26 24.8
*This data is for reference only.
The figures will vary with the application, so please confirm actual operating conditions before use.
Timing Waveforms
Example: the following shows the relationship between the input voltage VDD, the C
T
Terminal Voltage VCT and the output
voltage
VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Figure.15 and 16).
1
When the power supply is turned on, the output is unstable
from after over the operating limit voltage (V
OPL) until tPHL.
Therefore it is possible that the reset signal is not outputted when
the rise time of V
DD
is faster than tPHL.
2
When VDD is greater than VOPL but less than the reset release
voltage (V
DET+VDET), the C
T
terminal (VCT) and output (VOUT)
voltages will switch to L.
3
If VDD exceeds the reset release voltage (VDET+VDET), then
V
OUT switches from L to H (with a delay due to the C
T
terminal).
4
If VDD drops below the detection voltage (VDET) when the
power supply is powered down or when there is a power supply
fluctuation, V
OUT switches to L (with a delay of tPHL).
5
The potential difference between the detection voltage and the
release voltage is known as the hysteresis width (V
DET). The
system is designed such that the output does not toggle with
power supply fluctuations within this hysteresis width, preventing
malfunctions due to noise.
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q1
V
OUT
RESET
R
L
V
DD
Vref
V
DD
GND
CT
R1
R2
R3
Q3
Q2
V
OUT
RESET
Q1
V
DD
V
DD
-V
CTH
V
DD
VDD
VDET+ΔVDET
VDET
VOPL
0V
1/2 VDD
tPHL
①
tPLH
tPHL
tPLH
② ③ ④
CT
⑤
VOUT
Fig.17 Timing Waveform
