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74ALVCH32374BF

P1-P3P4-P6P7-P7
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
1
AUGUST 2009INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
©2009 Integrated Device Technology, Inc. DSC-4909/5
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
•VCC = 3.3V ± 0.3V, Normal Range
•VCC = 2.7V to 3.6V, Extended Range
•VCC = 2.5V ± 0.2V
• CMOS power levels (0.4
μμ
μμ
μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in 96-ball LFBGA package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for Heavy Loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
IDT74ALVCH32374
3.3V CMOS 32-BIT
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
DESCRIPTION:
This 32-bit edge-triggered D-type flip-flop is built using advanced dual
metal CMOS technology. This high-speed, low-power register is ideal for
use as a buffer register for data synchronization and storage. The Output
Enable (OE) and clock (CLK) controls are organized to operate the device
as four 8-bit registers, two 16-bit registers, or one 32-bit register with
common clock. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
The ALVCH32374 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH32374 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistor.
1
OE
D
C
1
CLK
1
D
1
1
Q
1
TO SEVEN OTHER CHANNELS
3
OE
D
C
3
CLK
3
D
1
3
Q
1
TO SEVEN OTHER CHANNELS
2
OE
D
C
2
CLK
2
D
1
2
Q
1
TO SEVEN OTHER CHANNELS
4
OE
D
C
4
CLK
4
D
1
4
Q
1
TO SEVEN OTHER CHANNELS
A3
A4
A5
H3
H4
E5
J3
J4
J5
T3
T4
N5
E2
A2
J2
N2
INDUSTRIAL TEMPERATURE RANGE
2
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
LFBGA
TOPVIEW
96 BALL LFBGA PACKAGE ATTRIBUTES
PIN CONFIGURATION
1.5mm Max.
1.4mm Nom.
1.3mm Min.
0.8mm
6
5
4
3
2
1
TOP VIEW
ABCDE FGHJKLMNPRT
ABC DEFGHJK LMNPRT
6
5
4
3
2
1
13.5mm
5.5mm
A
B
C
E
F
G
H
J
K
L
M
N
P
D
T
R
6
5
4
3
2
1
1
D
6
1
D
8
2
D
1
2
D
2
2
D
4
2
D
8
2
OE
1
D
4
1
D
5
1
D
7
2
D
6
2
D
7
2
D
3
2
D
5
1
D
2
1
D
3
1
D
1
GND
3
D
8
3
D
2
3
D
4
4
D
1
4
D
3
4
D
2
3
D
3
3
D
5
4
D
4
3
D
1
4
D
6
GND
GND
1
Q
1
V
CC
GND
V
CC
1
Q
2
1
Q
3
4
Q
6
4
Q
8
GND
GND
2
Q
2
2
Q
4
1
Q
4
1
Q
5
1
Q
7
2
Q
6
2
Q
7
3
Q
7
4
Q
2
3
Q
3
3
Q
5
4
Q
4
3
Q
1
1
Q
6
1
Q
8
2
Q
1
2
Q
8
2
Q
3
2
Q
5
3
Q
6
3
Q
8
3
Q
2
3
Q
4
4
Q
1
4
Q
3
GND
V
CC
GND
V
CC
GND
GND
V
CC
GND
GND
V
CC
GND
V
CC
3
D
7
3
D
6
1
OE
1
CLK
3
CLK
4
D
5
4
D
8
4
D
7
4
OE
4
Q
7
4
Q
5
V
CC
GND
GND
3
OE
2
CLK
GND
4
CLK
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3
Pin Names Description
xDx Data Inputs
(1)
xCLK Clock Inputs
xQx 3-State Outputs
xOE 3-State Output Enable Inputs (Active LOW)
PIN DESCRIPTION
Symbol Description Max Unit
VTERM
(2)
Terminal Voltage with Respect to GND –0.5 to +4.6 V
VTERM
(3)
Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V
TSTG Storage Temperature –65 to +150 ° C
IOUT DC Output Current –50 to +50 mA
I
IK Continuous Clamp Current, ±50 mA
VI < 0 or VI > VCC
IOK Continuous Clamp Current, VO < 0 –50 mA
I
CC Continuous Current through each ±100 mA
ISS VCC or GND
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC terminals.
3. All terminals except VCC.
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
FUNCTION TABLE (EACH FLIP-FLOP)
(1)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
2. Output level of Q before the indicated steady-state conditions were established.
Inputs Outputs
xOE xCLK xDx xQx
L ↑ HH
L ↑ LL
L H or L X Q
(2)
HX X Z
NOTE:
1. As applicable to the device type.
Symbol Parameter
(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 5 7 pF
COUT Output Capacitance VOUT = 0V 7 9 pF
C
I/O I/O Port Capacitance VIN = 0V 7 9 pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
P1-P3P4-P6P7-P7

74ALVCH32374BF

Mfr. #:
Buy 74ALVCH32374BF
Manufacturer:
IDT
Description:
Flip Flops 3.3V FAST CMOS 18BIT
Lifecycle:
New from this manufacturer.
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