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74ALVCH32374BF

P1-P3P4-P6P7-P7
INDUSTRIAL TEMPERATURE RANGE
4
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Symbol Parameter Test Conditions Min. Typ.
(1)
Max. Unit
VIH Input HIGH Voltage Level VCC = 2.3V to 2.7V 1.7 — — V
VCC = 2.7V to 3.6V 2 — —
V
IL Input LOW Voltage Level VCC = 2.3V to 2.7V — — 0.7 V
VCC = 2.7V to 3.6V — — 0.8
IIH Input HIGH Current VCC = 3.6V VI = VCC —— ±5µA
IIL Input LOW Current VCC = 3.6V VI = GND — — ±5µA
IOZH High Impedance Output Current VCC = 3.6V VO = VCC ——±10 µ A
IOZL (3-State Output pins) VO = GND — — ±10
VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V
VH Input Hysteresis VCC = 3.3V — 100 — mV
I
CCL Quiescent Power Supply Current VCC = 3.6V — 0.1 40 µA
ICCH VIN = GND or VCC
ICCZ
ΔICC Quiescent Power Supply Current One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µ A
Variation
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol Parameter
(1)
Test Conditions Min. Typ.
(2)
Max. Unit
IBHH Bus-Hold Input Sustain Current VCC = 3V VI = 2V – 75 — — µ A
IBHL VI = 0.8V 75 — —
IBHH Bus-Hold Input Sustain Current VCC = 2.3V VI = 1.7V – 45 — — µA
IBHL VI = 0.7V 45 — —
IBHHO Bus-Hold Input Overdrive Current VCC = 3.6V VI = 0 to 3.6V — — ±500 µ A
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
5
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V
Symbol Parameter Test Conditions Typical Typical Unit
CPD Power Dissipation Capacitance Outputs enabled CL = 0pF, f = 10Mhz 62 60 pF
CPD Power Dissipation Capacitance Outputs disabled 32 36
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS
(1)
VCC = 2.5V ± 0.2V VCC = 2.7V VCC = 3.3V ± 0.3V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fMAX 150 — 150 — 150 — M Hz
t
PLH Propagation Delay 1 5.3 — 4.9 1 4.2 ns
tPHL xCLK to xQx
t
PZH Output Enable Time 1 6.2 — 5.9 1 4.8 ns
tPZL xOE to xQx
tPHZ Output Disable Time 1 5.3 — 4.7 1.2 4.3 ns
tPLZ xOE to xQx
tSU Setup Time, data before CLK↑ 2.1 — 2.2 — 1.9 — ns
tH Hold Time, data after CLK↑ 0.6 — 0.5 — 0.5 — ns
tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns
t
SK(O) Output Skew
(2)
— ————500ps
NOTE:
1. V
IH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Test Conditions
(1)
Min. Max. Unit
VOH Output HIGH Voltage VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — V
V
CC = 2.3V IOH = – 6mA 2 —
V
CC = 2.3V IOH = – 12mA 1.7 —
V
CC = 2.7V 2.2 —
V
CC = 3V 2.4 —
VCC = 3V IOH = – 24mA 2 —
V
OL Output LOW Voltage VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 V
V
CC = 2.3V IOL = 6mA — 0.4
I
OL = 12mA — 0.7
V
CC = 2.7V IOL = 12mA — 0.4
VCC = 3V IOL = 24mA — 0.55
INDUSTRIAL TEMPERATURE RANGE
6
IDT74ALVCH32374
3.3V CMOS 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Open
V
LOAD
GND
V
CC
Pulse
Generator
D.U.T.
500Ω
500Ω
C
L
R
T
V
IN
V
OUT
(1, 2)
ALVC Link
INPUT
V
IH
0V
V
OH
V
OL
t
PLH1
t
SK
(x)
OUTPUT 1
OUTPUT 2
t
PHL1
t
SK
(x)
t
PLH2
t
PHL2
V
T
V
T
V
OH
V
T
V
OL
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
ALVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
0V
V
OH
V
OL
t
PLH
t
PHL
t
PHL
t
PLH
OUTPUT
VIH
VT
VT
VIH
VT
ALVC Link
DATA
INPUT
0V
0V
0V
0V
t
REM
TIMING
INPUT
SYNCHRONOUS
CONTROL
t
SU
t
H
t
SU
t
H
V
IH
V
T
V
IH
V
T
V
IH
V
T
V
IH
V
T
ALVC Link
ASYNCHRONOUS
CONTROL
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
V
T
t
W
V
T
ALVC Link
CONTROL
INPUT
t
PLZ
0V
OUTPUT
NORMALLY
LOW
t
PZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
t
PHZ
0V
V
LZ
V
OH
V
T
V
T
t
PZL
V
LOAD/2
V
LOAD/2
V
IH
V
T
V
OL
V
HZ
ALVC Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Output Skew - tSK(X)
Pulse Width
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Symbol VCC
(1)
= 3.3V±0.3V VCC
(1)
= 2.7V VCC
(2)
= 2.5V±0.2V Unit
VLOAD 6 6 2 x Vcc V
VIH 2.7 2.7 Vcc V
VT 1.5 1.5 Vcc / 2 V
VLZ 300 300 150 mV
VHZ 300 300 150 mV
C
L 50 50 30 pF
TEST CONDITIONS
SWITCH POSITION
Test Switch
Open Drain
Disable Low V
LOAD
Enable Low
Disable High GND
Enable High
All Other Tests Open
P1-P3P4-P6P7-P7

74ALVCH32374BF

Mfr. #:
Buy 74ALVCH32374BF
Manufacturer:
IDT
Description:
Flip Flops 3.3V FAST CMOS 18BIT
Lifecycle:
New from this manufacturer.
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