MAX9725
Component Selection
Input Filtering
The AC-coupling capacitor (C
IN
) and an internal gain-
setting resistor form a highpass filter that removes any
DC bias from an input signal (see the
Functional
Diagrams
). C
IN
allows the MAX9725A–MAX9725D to
bias the signal to an optimum DC level. The -3dB point
of the highpass filter, assuming zero source imped-
ance, is given by:
Choose C
IN
so f
-3dB
is well below the lowest frequency of
interest. R
IN
for the MAX9725A–MAX9725D is 25kΩ and a
minimum of 10kΩ for the MAX9725E. Setting f
-3dB
too
high affects the amplifier’s low-frequency response. Use
capacitors with low-voltage coefficient dielectrics. Film or
C0G dielectric capacitors are good choices for AC-cou-
pling capacitors. Capacitors with high-voltage coeffi-
cients, such as ceramics, can result in increased
distortion at low frequencies.
Charge-Pump Capacitor Selection
Use capacitors with less than 100mΩ of ESR. Low-ESR
ceramic capacitors minimize the output impedance of the
charge pump. Capacitors with an X7R dielectric provide
the best performance over the extended temperature
range. Table 1 lists suggested capacitor manufacturers.
Flying Capacitor (C1)
The value of C1 affects the charge pump’s load regula-
tion and output impedance. Choosing C1 too small
degrades the MAX9725’s ability to provide sufficient
current drive and leads to a loss of output voltage.
Increasing the value of C1 improves load regulation
and reduces the charge-pump output impedance. See
the Output Power vs. Charge-Pump Capacitance and
Load Resistance graph in the
Typical Operating
Characteristics
.
Hold Capacitor (C2)
The hold capacitor’s value and ESR directly affect the
ripple at PV
SS
. Increasing the value of C2 reduces rip-
ple. Choosing a capacitor with lower ESR reduces rip-
ple and output impedance. Lower capacitance values
can be used in systems with low maximum output
power levels. See the Output Power vs. Charge-Pump
Capacitance and Load Resistance graph in the
Typical
Operating Characteristics
.
Power-Supply Bypass Capacitor (C3)
The power-supply bypass capacitor (C3) lowers the
output impedance of the power supply and reduces the
impact of the MAX9725’s charge-pump switching tran-
sients. Bypass V
DD
to PGND with the same value as
C1. Place C3 as close to V
DD
as possible.
Layout and Grounding
Proper layout and grounding are essential for optimum
performance. Connect PGND and SGND together at a
single point on the PC board. Connect PV
SS
to SV
SS
and bypass with C2 to PGND. Bypass V
DD
to PGND
with C3. Place capacitors C2 and C3 as close to the
MAX9725 as possible. Route PGND, and all traces that
carry switching transients, away from SGND and the
audio signal path.
The MAX9725 does not require additional heatsinking.
The thin QFN package features an exposed paddle that
improves thermal efficiency of the package. Ensure the
exposed paddle is electrically isolated from GND and
V
DD
. Connect the exposed paddle to V
SS
if necessary.
UCSP Applications Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board techniques, bump-pad layout , and recommend-
ed reflow temperature profile, as well as the latest infor-
mation on reliability testing results, go to Maxim’s
website at www.maxim-ic.com/ucsp for the
Application Note 1891:
Wafer-Level Packaging (WLP)
and Its Applications
.
