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TJA1044GTK/3Z

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
TJA1044 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 24 August 2017 7 of 27
NXP Semiconductors
TJA1044
High-speed CAN transceiver with Standby mode
Dominant or recessive bits between the above mentioned phases that are shorter than
t
wake(busdom)
and t
wake(busrec)
respectively are ignored.
The complete dominant-recessive-dominant pattern must be received within t
to(wake)bus
to
be recognized as a valid wake-up pattern (see Figure 3
). Otherwise, the internal wake-up
logic is reset. The complete wake-up pattern will then need to be retransmitted to trigger a
wake-up event. Pin RXD remains HIGH until the wake-up event has been triggered.
After a wake-up sequence has been detected, the TJA1044 will remain in Standby mode
with the bus signals reflected on RXD. Note that dominant or recessive phases lasting
less than t
fltr(wake)bus
will not be detected by the low-power differential receiver and will not
be reflected on RXD in Standby mode.
A wake-up event is not flagged on RXD if any of the following events occurs while a valid
wake-up pattern is being received:
• The TJA1044 switches to Normal mode
• The complete wake-up pattern was not received within t
to(wake)bus
• A V
CC
or V
IO
undervoltage is detected (V
CC
< V
uvd(swoff)(VCC)
or V
IO
< V
uvd(swoff)(VIO)
;
see Section 7.3.3
)
7.3 Fail-safe features
7.3.1 TXD dominant time-out function
A 'TXD dominant time-out' timer is started when pin TXD is set LOW. If the LOW state on
this pin persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of
approximately 25 kbit/s.
Fig 3. Wake-up timing
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TJA1044 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 24 August 2017 8 of 27
NXP Semiconductors
TJA1044
High-speed CAN transceiver with Standby mode
7.3.2 Internal biasing of TXD and STB input pins
Pins TXD and STB have internal pull-ups to V
CC
(V
IO
for variants with a V
IO
pin) to ensure
a safe, defined state in case one or both of these pins are left floating. Pull-up currents
flow in these pins in all states; both pins should be held HIGH in Standby mode to
minimize supply current.
7.3.3 Undervoltage detection on pins V
CC
and V
IO
If V
CC
drops below the standby undervoltage detection level, V
uvd(stb)(VCC)
, the transceiver
switches to Standby mode. The logic state of pin STB is ignored until V
CC
has recovered.
In versions with a V
IO
pin, if V
IO
drops below the switch-off undervoltage detection level
(V
uvd(swoff)(VIO)
), the transceiver switches off and disengages from the bus (zero load) until
V
IO
has recovered.
In versions without a V
IO
pin, if V
CC
drops below the switch-off undervoltage detection
level (V
uvd(swoff)(VCC)
), the transceiver switches off and disengages from the bus (zero
load) until V
CC
has recovered.
7.3.4 Overtemperature protection
The output drivers are protected against overtemperature conditions. If the virtual junction
temperature exceeds the shutdown junction temperature, T
j(sd)
, both output drivers are
disabled. When the virtual junction temperature drops below T
j(sd)
again, the output
drivers recover once TXD has been reset to HIGH. Including the TXD condition prevents
output driver oscillation due to small variations in temperature.
7.4 V
IO
supply pin (TJA1044x/3 variants)
Pin V
IO
should be connected to the microcontroller supply voltage (see Figure 7). This will
adjust the signal levels of pins TXD, RXD and STB to the I/O levels of the microcontroller.
Pin V
IO
also provides the internal supply voltage for the low-power differential receiver in
the transceiver. For applications running in low-power mode, this allows the bus lines to
be monitored for activity even if there is no supply voltage on pin V
CC
.
For variants of the TJA1044 without a V
IO
pin, all circuitry is connected to V
CC
(pin 5 is not
bonded). The signal levels of pins TXD, RXD and STB are then compatible with 5 V
microcontrollers. This allows the device to interface with both 3.3 V and 5 V-supplied
microcontrollers, provided the microcontroller I/Os are 5 V tolerant.
TJA1044 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 6 — 24 August 2017 9 of 27
NXP Semiconductors
TJA1044
High-speed CAN transceiver with Standby mode
8. Limiting values
[1] The device can sustain voltages up to the specified values over the product lifetime, provided applied voltages (including transients)
never exceed these values.
[2] Maximum voltage should never exceed 7 V.
[3] V
CC
+ 0.3 in the non-V
IO
product variants TJA1044T/TJA1044GT/TJA1044GTK.
[4] According to IEC TS 62228 (2007), Section 4.2.4; parameters for standard pulses defined in ISO7637 part 2: 2004-06.
[5] According to IEC TS 62228 (2007), Section 4.3; DIN EN 61000-4-2.
[6] According to AEC-Q100-002.
[7] According to AEC-Q100-003.
[8] According to AEC-Q100-011 Rev-C1. The classification level is C4B.
[9] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T
vj
=T
amb
+P R
th(vj-a)
, where R
th(vj-a)
is a
fixed value to be used for the calculation of T
vj
. The rating for T
vj
limits the allowable combinations of power dissipation (P) and ambient
temperature (T
amb
).
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
Symbol Parameter Conditions Min Max Unit
V
x
voltage on pin x
[1]
on pins CANH, CANL 42 +42 V
on pin V
CC
, V
IO
0.3 +7 V
on any other pin
[2]
0.3 V
IO
+ 0.3
[3]
V
V
(CANH-CANL)
voltage between pin CANH and
pin CANL
27 +27 V
V
trt
transient voltage on pins CANH and CANL
[4]
pulse 1 100 - V
pulse 2a - 75 V
pulse 3a 150 - V
pulse 3b - 100 V
V
ESD
electrostatic discharge voltage IEC 61000-4-2 (150 pF, 330 )
[5]
on pins CANH and CANL 8+8 kV
Human Body Model (HBM); 100 pF, 1.5 k
[6]
on pins CANH and CANL 8+8 kV
on any other pin 4+4 kV
Machine Model (MM); 200 pF, 0.75 H, 10
[7]
on any pin 200 +200 V
Charged Device Model (CDM); field Induced
charge; 4 pF
[8]
on corner pins 750 +750 V
on any other pin 500 +500 V
T
vj
virtual junction temperature
[9]
40 +150 C
T
stg
storage temperature 55 +150 C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

TJA1044GTK/3Z

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Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC TJA1044GTK/HVSON8//3/REEL 13 Q1 NDP SSB
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