7
Figure 6. Recommended Interface Circuit
Application Information
The Applications Engineering Group at Avago Tech-
nologies is available to assist you with technical under-
standing and design trade-os associated with these
transceivers. You can contact them through your Avago
Technologies sales representative.
The following information is provided to answer some
of the most common questions about the use of the
parts.
Optical Power Budget and Link Penalties
The worst-case Optical Power Budget (OPB) in dB for a
ber-optic link is determined by the dierence between
the minimum transmitter output optical power (dBm
avg) and the lowest receiver sensitivity (dBm avg). This
OPB provides the necessary optical signal range to es-
tablish a working ber-optic link. The OPB is allocated
for the ber-optic cable length and the corresponding
link penalties. For proper link performance, all penalties
that aect the link performance must be accounted for
within the link optical power budget.
Electrical and Mechanical Interface
Recommended Circuit
Figure 6 shows the recommended interface for deploy-
ing the Avago Technologies transceivers in a +3.3 V
system.
o
V
EE
RX
o
V
CC
RX
o
SD
o
RD-
o
RD+
Z = 50
Z = 50
Z = 50
Z = 50
SD
LVTTL
V
CC
(+3.3 V)
V
CC
(+3.3 V)
RD+
RD-
TD-
o
TD+
o
T
DIS
o
V
EE
TX
o
V
CC
TX
o
1 µH
C2
1 µH
C1
C3
10 µF
T
X
R
X
100
130
130
T
DIS
(LVTTL)
12 345
10 9876
TD-
TD+
Note: C1 = C2 = C3 = 10 nF or 100 nF
TD+, TD- INPUTS ARE INTERNALLY TERMINATED AND AC COUPLED.
RD+, RD- OUTPUTS ARE INTERNALLY BIASED AND AC COUPLED.
Note A: CIRCUIT ASSUMES OPEN EMITTER OUTPUT.
Note B: CIRCUIT ASSUMES HIGH IMPENDANCE INTERNAL BIAS @ V
CC
- 1.3 V.
NOTE A
NOTE B
V
CC
(+3.3 V)
10 µF
8
Data Line Interconnections
Avago Technologies AFCT-5943xxZ ber-optic trans-
ceivers are designed to couple to +3.3 V PECL signals.
The transmitter driver circuit regulates the output
optical power. The regulated light output will maintain
a constant output optical power provided the data
pattern is balanced in duty cycle. If the data duty cycle
has long, continuous state times (low or high data duty
cycle), then the output optical power will gradually
change its average output optical power level to its pre-
set value.
The AFCT-5943xxZ has a transmit disable function
which is a single-ended +3.3 V TTL input which is dc-
coupled to pin 8.
The receiver section is internally ac-coupled between
the pre amplier and the post-amplier stages. The Data
and Data-bar outputs of the post-amplier are inter-
nally biased and ac-coupled to their respective output
pins (pins 4, 5).
Signal Detect is a single-ended, +3.3 V TTL compatible
output signal that is dc-coupled to pin 3 of the module.
Signal Detect should not be ac-coupled externally to
the follow-on circuits because of its infrequent state
changes.
Caution should be taken to account for the proper in-
tercon-nection between the supporting Physical Layer
integrated circuits and these transceivers. Figure 6 il-
lustrates a recommended interface circuit for intercon-
necting to a +3.3 V dc PECL ber-optic transceiver.
Power Supply Filtering and Ground Planes
It is important to exercise care in circuit board layout to
achieve optimum performance from these transceivers.
Figure 6 shows the power supply circuit which complies
with the small form factor multisource agreement. It is
further recommended that a continuous ground plane
be provided in the circuit board directly under the
transceiver to provide a low inductance ground for sig-
nal return current. This recommendation is in keeping
with good high frequency board layout practices.
Package footprint and front panel considerations
The Avago Technologies transceivers comply with the
circuit board Common Transceiver Footprint” hole
pattern dened in the current multisource agreement
which dened the 2 x 5 package style. This drawing
is reproduced in Figure 7 with the addition of ANSI
Y14.5M compliant dimensioning to be used as a guide
in the mechanical layout of your circuit board. Figure 8
shows the front panel dimensions associated with such
a layout.
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the
event of a single fault failure, the transmit-ter must ei-
ther maintain eye-safe operation or be disabled.
The AFCT-5943xxZ is intrinsically eye safe and does not
require shut down circuitry.
Signal Detect
The Signal Detect circuit provides a deasserted output
signal when the optical link is broken (or when the
remote transmitter is OFF). The Signal Detect thresh-
old is set to transition from a high to low state be-
tween the minimum receiver input optical power and
-35 dBm avg. input optical power indicating a denite
optical fault (e.g. unplugged connector for the receiver
or transmitter, broken ber, or failed far-end transmit-
ter or data source). The Signal Detect does not detect
receiver data error or error-rate. Data errors can be
determined by signal processing oered by upstream
PHY ICs.
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from electronic
equipment. Success in controlling generated Electro-
magnetic Interference (EMI) enables the designer to pass
a governmental agency’s EMI regulatory standard and
more importantly, it reduces the possibility of interfer-
ence to neighboring equipment. Avago Technologies
has designed the AFCT-5943xxZ to provide good EMI
performance. The EMI performance of a chassis is de-
pendent on physical design and features which help im-
prove EMI suppression. Avago Technologies encourages
using standard RF suppression practices and avoiding
poorly EMI-sealed enclosures.
Avago Technologies OC-48 LC transceivers (AFCT-
5943xxZ) have nose shields which provide a convenient
chassis connection to the nose of the transceiver. This
nose shield and the underlying metalization (except
‘G’ options) improve system EMI performance by eec-
tively closing o the LC aperture. The recommended
transceiver position, PCB layout and panel opening for
both devices are the same, making them mechanically
drop-in compatible. Figure 8 shows the recommended
positioning of the transceivers with respect to the PCB
and faceplate.
9
Figure 8. Recommended Panel Mounting
Figure 7. Recommended Board Layout Hole Pattern
NOTES:
1. THIS FIGURE DESCRIBES MSA RECOM-
MENDED CIRCUIT BOARD LAYOUT FOR
THE SFF TRANSCEIVER.
2. THE HATCHED AREAS ARE KEEP-OUT
AREAS RESERVED FOR HOUSING
STANDOFFS. NO METAL TRACES OR
GROUND CONNECTION IN KEEP-OUT
AREAS.
3. 2 x 5 TRANSCEIVER MODULE REQUIRES
12 PCB HOLES (10 I/O PINS, 2 SOLDER
POSTS). SOLDER POSTS SHOULD BE
CONNECTED TO SIGNAL GROUND.
*4. THE MOUNTING STUDS SHOULD BE
SOLDERED TO CHASSIS GROUND FOR
MECHANICAL INTEGRITY AND TO ENSURE
FOOTPRINT COMPATIBILITY WITH OTHER
SFF TRANSCEIVERS.
*5. HOLES FOR OPTIONAL HOUSING LEADS
MUST BE TIED TO SIGNAL GROUND.
7.59
(0.299)
3
(0.118)
3
(0.118)
6
(0.236)
4.57
(0.18)
4 x 1.78
(0.07)
10 x Ø 0.81 ±0.1
(0.032 ±0.004)
3.08
(0.121)
2 x Ø 2.29
(0.09)
9.59
(0.378)
2
(0.079)
13.34
(0.525)
7.11
(0.28)
4 x Ø 1.4 ±0.1
(0.055 ±0.004)
2 x Ø 1.4 ±0.1
(0.055 ±0.004)
2 x Ø 1.4 ±0.1
(0.055 ±0.004)
10.16
(0.4)
3.56
(0.14)
2 x Ø 2.29 MAX.
(0.09)
17.8
(0.700)
2
(0.079)
*4
*5
15.24
(0.6)
DIMENSIONS IN MILLIMETERS (INCHES)
1. FIGURE DESCRIBES THE RECOMMENDED FRONT PANEL OPENING FOR A LC OR SG SFF TRANSCEIVER.
2. SFF TRANSCEIVER PLACED AT 15.24 mm (0.6) MIN. SPACING.
14.22 ±0.1
(0.56 ±0.004)
10.16 ±0.1
(0.4 ±0.004)
DETAIL A
TOP OF PCB
1
(0.039)
A
SOLDER POSTS
15.75 MAX. 15.0 MIN.
(0.62 MAX. 0.59 MIN.)
SECTION B  B
15.24
(0.6)
B
B

AFCT-5943LZ

Mfr. #:
Manufacturer:
Description:
Fiber Optic Transmitters, Receivers, Transceivers Transceive
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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