ATMEGA644RFR2-ZU

Spectrum Signal (DSSS) processing with spreading and despreading. The device is

fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards.

The ATmega2564/1284/644RFR2 provides the following features: 256K/128K/64K

Watchdog Timer with Internal Oscillator, a SPI serial port, IEEE std. 1149.1 compliant

JTAG test interface, also used for accessing the On-chip Debug system and

programming and 6 software selectable power saving modes.

The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and

interrupt system to continue functioning. The Power-down mode saves the register

contents but freezes the Oscillator, disabling all other chip functions until the next

interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to

run, allowing the user to maintain a timer base while the rest of the device is sleeping.

The ADC Noise Reduction mode stops the CPU and all I/O modules except

asynchronous timer and ADC, to minimize switching noise during ADC conversions. In

The transmit output power is set to maximum. If the radio transceiver is in SLEEP mode

the current is dissipated by the AVR microcontroller only.

In Deep Sleep mode all major digital blocks with no data retention requirements are

disconnected from main supply providing a very small leakage current. Watchdog timer,

MAC symbol counter and 32.768kHz oscillator can be configured to continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology.

on on-chip boot program running on the AVR core. The boot program can use any

section is updated, providing true Read-While-Write operation. By combining an 8 bit

flexible and cost effective solution to many embedded control applications.

system development tools including: C compiler, macro assemblers, program

debugger/simulators, in-circuit emulators, and evaluation kits.

External analog supply voltage.

External digital supply voltage.

Regulated analog supply voltage (internally generated).

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also provides functions of various special features of the

ATmega2564/1284/644RFR2.

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

Internally Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected

for each bit). The Port E output buffers have symmetrical drive characteristics with both

high sink and source capability. As inputs, Port E pins that are externally pulled low will

source current if the pull-up resistors are activated. The Port E pins are tri-stated when

a reset condition becomes active, even if the clock is not running.

Due to the low pin count of the QFN48 package port E6 is not connected to a pin.

Port E also provides functions of various special features of the

ATmega2564/1284/644RFR2.

high sink and source capability. As inputs, Port F pins that are externally pulled low will

source current if the pull-up resistors are activated. The Port F pins are tri-stated when

a reset condition becomes active, even if the clock is not running.

Due to the low pin count of the QFN48 package port F3 and F4 are connected to the

same pin. The I/O configuration should be done carefully in order to avoid excessive

power dissipation.

Port F also provides functions of various special features of the

ATmega2564/1284/644RFR2.

reduced compared to the other port pins. The output voltage drop (V

, V

) is higher

while the leakage current is smaller. As inputs, Port G pins that are externally pulled low