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RFR2
3.2.19 TST
Programming and test mode enable pin. If pin TST is not used pull it to low.
3.2.20 CLKI
Input to the clock system. If selected, it provides the operating clock of the
microcontroller.
3.3 Unused Pins
Floating pins can cause power dissipation in the digital input stage. They should be
connected to an appropriate source. In normal operation modes the internal pull-up
resistors can be enabled (in Reset all GPIO are configured as input and the pull-up
resistors are still not enabled).
Bi-directional I/O pins shall not be connected to ground or power supply directly.
The digital input pins TST and CLKI must be connected. If unused pin TST can be
connected to AVSS while CLKI should be connected to DVSS.
Output pins are driven by the device and do not float. Power supply pins respective
ground supply pins are connected together internally.
XTAL1 and XTAL2 shall never be forced to supply voltage at the same time.
3.4 Compatibility and Feature Limitations of QFN-48 Package
3.4.1 AREF
The reference voltage output of the A/D converter is not connected to a pin in the
ATmega2564/1284/644RFR2.
3.4.2 Port E6
The port E6 is not connected to a pin in the ATmega2564/1284/644RFR2. The alternate
pin functions as clock input to timer 3 and external interrupt 6 are not available.
3.4.3 Port F3 and F4
The port F3 and F4 are connected to the same pin in the ATmega2564/1284/644RFR2.
The output configuration should be done carefully in order to avoid excessive current
consumption.
The alternate pin function of port F4 is used by the JTAG interface. If the JTAG
interface is used the port F3 must be configured as input and the alternate pin function
output DIG4 (RX/TX indicator) must be disabled. Otherwise the JTAG interface will not
work. The SPIEN Fuse should be programmed in order to be able to erase a program
that accidentally drive port F3.
There are just 7 single-ended input channel to the ADC available.
3.4.4 Port G0
The port G0 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function DIG3 (inverted RX/TX indicator) is not available. If the JTAG
interface is not used the DIG4 alternate pin function output of port F3 can still be used
as RX/TX indicator.
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3.4.5 Port G2
The port G2 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function AMR (asynchronous automated meter reading input to timer 2) is
not available.
3.4.6 Port G5
The port G5 is not connected to a pin in the ATmega2564/1284/644RFR2. The
alternate pin function OC0B (output compare channel of 8-Bit timer 0) is not available.
3.4.7 RSTON
The RSTON reset output signaling the internal reset state is not connected to a pin in
the ATmega2564/1284/644RFR2.
3.5 Configuration summary
According to the application requirements a variable memory size allows to optimize
current consumption and leakage current.
Table 3-1 Memory Configuration
Device Flash EEPROM SRAM
ATmega2564RFR2 256KB 8KB 32KB
ATmega1284RFR2 128KB 4KB 16KB
ATmega644RFR2 64KB 2KB 8KB
Package and associated pin configuration are the same for all devices providing full
functionality to the application.
Table 3-2 System Configuration
Device Package GPIO Serial IF ADC channel
ATmega2564RFR2 QFN48 33 2 USART, SPI, TWI 7
ATmega1284RFR2 QFN48 33 2 USART, SPI, TWI 7
ATmega644RFR2 QFN48 33 2 USART, SPI, TWI 7
The devices are optimized for applications based on the ZigBee and the IEEE 802.15.4
specification. Having application stack, network layer, sensor interface and an excellent
power control combined in a single chip many years of operation should be possible.
Table 3-3 Application Profile
Device Application
ATmega2564RFR2 Large Network Coordinator / Router for IEEE 802.15.4 / ZigBee Pro
ATmega1284RFR2 Network Coordinator / Router for IEEE 802.15.4
ATmega644RFR2 End node device / network processor
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RFR2
4 Application Circuits
4.1 Basic Application Schematic
A basic application schematic of the ATmega2564/1284/644RFR2 with a single-ended
RF connector is shown in Figure 4-1 below and the associated Bill of Material in Table
4-1 on page 10. The 50 single-ended RF input is transformed to the 100 differential
RF port impedance using Balun B1. The capacitors C1 and C2 provide AC coupling of
the RF input to the RF port, capacitor C4 improves matching.
Figure 4-1. Basic Application schematic (48-pin package)
6
5
4
3
2
1
13 14 15 16 17 18 19 20
4041424344454647
PF0
AVSS
RFP
RFN
AVSS
TST
DVSS
DVDD
XTAL2
DEVDD
AVDD
EVDD
AVSS
XTAL1
31
32
33
34
35
36
PE0
CB3
CB4
RSTN
V
DD
XTAL
CX1 CX2
CB1
V
DD
CB2
B1
RF
C4
21 22 23 24
12
11
10
9
8
7
48 3839 37
25
26
27
28
29
30
XTAL
32kHz
CX3 CX4
CLKI
PB0
PB7
PE7
PE5
PF7
PG1
PD0
Pins TST & CLKI
must be connected
PG3
PD7
PG4
PF3/4
C1
The power supply bypass capacitors (CB2, CB4) are connected to the external analog
supply pin (EVDD, pin 44) and external digital supply pin (DEVDD, pin 16). The
capacitor C1 provides the required AC coupling of RFN/RFP.
Floating pins can cause excessive power dissipation (e.g. during power on). They
should be connected to an appropriate source. GPIO shall not be connected to ground
or power supply directly.
The digital input pins TST and CLKI must be connected. If pin TST will never be used it
can be connected to AVSS while an unused pin CLKI could be connected to DVSS (see
chapter "Unused Pins" on page 7).
Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital
voltage regulators to ensure stable operation and to improve noise immunity.
Capacitors should be placed as close as possible to the pins and should have a low-
resistance and low-inductance connection to ground to achieve the best performance.

ATMEGA644RFR2-ZU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
RF Microcontrollers - MCU 2.4GHZ 802.15.4 64K SOC 48pin
Lifecycle:
New from this manufacturer.
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