HMC8325 Data Sheet
Rev. 0 | Page 12 of 16
THEORY OF OPERATION
The circuit architecture of the HMC8325 low noise amplifier is
shown in Figure 44. The HMC8325 uses four cascaded gain
stages to form an amplifier with a combined gain of 21 dB
(typical), a noise figure of 3.6 dB (typical), and 1 dBm (typical)
input IP3 across the 71 GHz to 86 GHz frequency range. Stage 1
and Stage 2 can be biased separately from Stage 3 and Stage 4.
Operating at V
D1
= V
D2
= 2 V and V
D3
= V
D4
= 4 V improves
gain and noise figure compared to V
D1
= V
D2
= V
D3
= V
D4
= 4 V.
The input IP3 is slightly lower for the V
D1
= V
D2
= 2 V and V
D3
=
V
D4
= 4 V case. A compromise bias voltage between the gain
noise figure vs. the input IP3 is V
D1
= V
D2
= V
D3
= V
D4
= 3 V.
Gain control can be achieved by down biasing Stage 3 and
Stage 4. By lowering the drain current of I
D3
and I
D4
, a 12 dB
reduction in gain can be achieved with a small degradation in
the noise figure. Refer to Figure 45 for further details on biasing
arrangements for the different stages.
14692-044
RF
OUT
RF
IN
Figure 44. Circuit Architecture
