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AK4388AET

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
[AK4388A]
MS1008-E-02 2010/09
- 13 -
■ Reset Function (MCLK, LRCK or BICK stop)
When the MCLK, LRCK or BICK stops, the digital circuit of the AK4388A is placed in power-down mode. When the
MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4388A returns to normal operation
mode.
Normal Operation
Internal
State
Digital Circuit Power-down
Normal Operation
GD GD
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(1)
(2)
External
MUTE
(5)
(1)
MCLK Stop
RSTN pin
Power-down
Power-down
(3) (3)
(3)
VCOM
(5)
Clock In
MCLK, BICK, LRCK
External
MUTE
(5)
LRCK Stop
<Case1:MCLK Stop>
<Case2:LRCK Stop>
(5) (5)
Clock In
MCLK, BICK, LRCK
External
MUTE
(5)
BICK Stop
<Case3:BICK Stop>
(5) (5)
(4)
Notes.
(1)
The analog output corresponding to a specific digital input has group delay (GD).
(2)
Digital data can be stopped. The click noise, after MCLK, LRCK and BICK are input again, can be reduced by
inputting the “0” data during this period.
(3)
Click noise occurs within 20usec or 20usec +3 ~ 4LRCK from the riding edge (“↑”) of the RSTN pin or MCLK
inputs. Click noise also occurs within 20usec when MCLK, LRCK or BICK is stopped.
(4)
The analog output becomes idle voltage when MCLK is stopped. It becomes VCOM voltage if LRCK or BICK is
stopped when MCLK is input.
(5)
Mute the analog output externally if click noise (3) adversely affect system performance.
Figure 10. Clock Stop Sequence
[AK4388A]
MS1008-E-02 2010/09
- 14 -
SYSTEM DESIGN
Figure 11 shows the system connection diagram. An evaluation board (AKD4388A) is available for fast evaluation as
well as suggestions for peripheral circuitry.
MCLK
1
BICK
2
SDTI
3
LRCK
4
RSTN
5
SMUTE
6
A
CKS
7
DIF0 8
DZF
16
DEM
15
VDD 14
VSS
13
VCOM
12
AOUTL
11
AOUTR
10
DIF1
9
Master Clock
AK4388A
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u
+
Rch Out
Lch Out
Analog GroundDigital Ground
A
nalog
Supply 5V
+
10u
Optional External
Mute Circuits
Mode
Setting
Figure 11. Typical Connection Diagram
Notes:
- LRCK = fs, BICK=64fs.
- When AOUT drives capacitive load, a resistor must be connected in series between AOUT and capacitive load.
- All input pins except DIF1 and DEM pins must not be left floating.
[AK4388A]
MS1008-E-02 2010/09
- 15 -
1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and must be separated from system digital supply. Decoupling capacitor,
especially 0.1μF ceramic capacitor, for high frequency should be placed as near to VDD as possible. The differential
voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are single-ended and centered on the VCOM voltage. The output signal range is typically 3.20Vpp
(typ@VDD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and
a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit).
The analog outputs have DC offsets of VCOM + a few mV. This DC offsets on analog outputs are eliminated by AC
coupling.
Figure 12 shows an example of the external LPF with 3.20Vpp (1.13Vrms) output. Figure 13 shows an
example of the external LPF with 2Vrms output.
AOUT
10u
220
2.2nF
AK4388A
22k
3.2Vpp (1.13Vrms)
Analog
Out
fc=328.8kHz, g=-0.064dB at 40kHz
Figure 12. External 1
st
order LPF Circuit Example (simple)
390p
3.9k
2.7k 3.9k
390p
+Vop
3.3k
-Vop
AOUT
10u
fc=125.8kHz, Q=0.752, g=0.058dB at 40kHz
Analog
Out
22k
AK4388A
5.93Vpp (2.09Vrms)
Figure 13. External 2
nd
order LPF Circuit Example (using op-amp with dual power supplies)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

AK4388AET

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