[AK4388A]
MS1008-E-02 2010/09
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OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4388A, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS pin = “L”, Normal Speed Mode), the frequency of MCLK is set automatically (
Table 1). In Auto Setting
Mode (ACKS pin = “H”), as MCLK frequency is detected automatically (
Table 2), and the internal master clock becomes
the appropriate frequency (
Table 3).
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 1152fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz
Table 1. System Clock Example (Manual Setting Mode, ACKS pin = “L”, Normal Speed Mode)
MCLK Mode Sampling Rate
1152fs Normal 8kHz~32kHz
512fs 768fs Normal 8kHz~48kHz
256fs 384fs Double 32kHz~96kHz
128fs 192fs Quad 120kHz~192kHz
Table 2. Sampling Speed (Auto Setting Mode, ACKS pin = “H”)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
32.0kHz - - 8.1920 12.2880 16.3840 24.5760 36.8640
44.1kHz - - 11.2896 16.9344 22.5792 33.8688 -
48.0kHz - - 12.2880 18.4320 24.5760 36.8640 -
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - -
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - -
Table 3. System Clock Example (Auto Setting Mode, ACKS pin = “H”)
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (
Table 2). When the
sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs.
ACKS pin MCLK DR,S/N
L 256fs/384fs/512fs/768fs 106dB
H 256fs/384fs 103dB
H 512fs/768fs 106dB
Table 4. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
