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9DB803DGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 10
ICS9DB803D REV N 071013
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Clock Periods–Differential Outputs with Spread Spectrum Disabled
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2,3
DIF 133
7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2,4
DIF 166
5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2,4
DIF 200
4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2,4
DIF 266
3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2,4
DIF 333
2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2,4
DIF 400
2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2,4
Notes
Definition
Units
Signal Name
Measurement
Window
Symbol
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
Lg- -SSC -ppm error 0ppm + ppm error +SSC Lg+
Absolute
Period
Short-term
Avera
g
e
Long-Term
Avera
g
e
Period
Long-Term
Avera
g
e
Short-term
Avera
g
e
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Minimum
Absolute
Period
Nominal Maximum Maximum Maximum
DIF 100
9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3
DIF 133
7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2,4
DIF 166
5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2,4
DIF 200
4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2,4
DIF 266
3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2,4
DIF 333
2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2,4
DIF 400
2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Driven by SRC output of main clock, PLL or Bypass mode
4
Driven by CPU output of CK410/CK505 main clock,
B
yp
ass mode onl
y
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with
CK409/CK410/CK505 accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
Notes
Measurement
Window
Units
Symbol
Definition
Signal Name
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 11
ICS9DB803D REV N 071013
Common Recommendations for Differential Routing Dimension or Value Unit Figure
L1 length, route as non-coupled 50ohm trace 0.5 max inch 1
L2 length, route as non-coupled 50ohm trace 0.2 max inch 1
L3 length, route as non-coupled 50ohm trace 0.2 max inch 1
Rs 33 ohm 1
Rt 49.9 ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max inch 1
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max inch 2
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max inch 2
SRC Reference Clock
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Down Device
REF_CLK Input
Figure 1: Down Device Routing
HCSL Output Buffer
L1
L1'
Rs
L2
L2'
Rs
L4'
L4
L3L3'
Rt Rt
PCI Express
Add-in Board
REF_CLK Input
Figure 2: PCI Express Connector Routing
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
IDT®
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2 12
ICS9DB803D REV N 071013
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b
Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

9DB803DGILFT

Mfr. #:
Buy 9DB803DGILFT
Manufacturer:
IDT
Description:
Clock Buffer 8 OUTPUT PCIE GEN2 BUFFER
Lifecycle:
New from this manufacturer.
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