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MC100EPT25DTG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 17
1 Publication Order Number:
MC100EPT25/D
MC100EPT25
-3.3V / -5V Differential
ECL to +3.3V LVTTL
Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small
outline 8-lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The V
BB
output allows the EPT25 to also be used in a single-ended
input mode. In this mode the V
BB
output is tied to the D input for
a inverting buffer or the D
input for a non-inverting buffer. If used, the
V
BB
pin should be bypassed to ground with at least a 0.01 mF
capacitor.
Features
• 1.1 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• Operating Range:
♦ V
CC
= 3.0 V to 3.6 V; V
EE
= −5.5 V to −3.0 V; GND = 0 V
• 24 mA TTL Outputs
• Q Output Will Default LOW with Inputs Open or at V
EE
• V
BB
Output
• Open Input Default State
• Safety Clamp on Inputs
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb-Free Package
ALYWG
G
KA25
1
8
www.onsemi.com
KPT25
ALYW
G
1
8
3V MG
G
14
(Note: Microdot may be in either location)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
ORDERING INFORMATION
Device Package Shipping
†
MC100EPT25DG SOIC−8NB
(Pb-Free)
98 Units/Tube
MC100EPT25DR2G SOIC−8NB
(Pb-Free)
2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EPT25DTR2G 2500/Tape & Reel
TSSOP−8
(Pb-Free)
MC100EPT25DTG 100 Units/Tube
DFN−8
(Pb-Free)
MC100EPT25MNR4G 1000/Tape & Reel
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAMS*
SOIC−8NB
D SUFFIX
CASE
751−07
TSSOP−8
DT SUFFIX
CASE
948R−02
1
8
1
8
DFN−8
MN SUFFIX
CASE 506AA
MC100EPT25
www.onsemi.com
2
1
2
3
45
6
7
8
Q
GND
V
CC
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
D
NCD
V
BB
V
EE
LVTTL
LVECL/ECL
Table 1. PIN DESCRIPTION
PIN
Q
D*, D
* Differential ECL Input Pair
FUNCTION
LVTTL Output
V
CC
V
BB
Output Reference Voltage
Positive Supply
GND Ground
V
EE
Negative Supply
NC No Connect
* Pins will default LOW when left open.
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND) or
leave unconnected, floating open.
EP
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor N/A
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC−8NB
TSSOP−8
DFN−8
Level 1
Level 3
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
Transistor Count 111 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MC100EPT25
www.onsemi.com
3
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V V
EE
= −5.0 V 3.8 V
V
EE
Negative Power Supply GND = 0 V V
CC
= +3.3 V −6 V
V
IN
Input Voltage GND = 0 V 0 to V
EE
V
I
BB
V
BB
Sink/Source ± 0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8NB 190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8NB 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8 185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN−8 129
84
°C/W
T
sol
Wave Solder (Pb-Free) <2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN−8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 4. NECL DC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= −5.5 V to −3.0 V; GND = 0.0 V (Note 1))
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
IEE
Power Supply Current 8.0 16 25 8.0 16 25 8.0 16 25 mA
V
IH
Input HIGH Voltage Single-Ended −1225 −880 −1225 −880 −1225 −880 mV
V
IL
Input LOW Voltage Single-Ended −1945 −1625 −1945 −1625 −1945 −1625 mV
V
BB
Output Voltage Reference −1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 2)
V
EE
+ 2.0 0.0 V
EE
+ 2.0 0.0 V
EE
+ 2.0 0.0 V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current 0.5 0.5 0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input parameters vary 1:1 with GND.
2. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
P1-P3P4-P6P7-P8

MC100EPT25DTG

Mfr. #:
Buy MC100EPT25DTG
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels Diff LVECL/ECL to LVTTL
Lifecycle:
New from this manufacturer.
Delivery:
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