10
FN8163.2
August 30, 2006
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V
H
/R
H
–V
L
/R
L
)/63, single pot
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated. These parameters are
periodically sampled and not 100% tested.
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V
CC
, then the potentiometer pins. It is suggested that V
CC
reach 90% of its final value before power is applied to the potentiometer pins. The V
CC
ramp rate specification should
be met, and any glitches or slope changes in the V
CC
line should be held to <100mV if possible. Also, V
CC
should not
reverse polarity by more than 0.5V.
Symbol Parameter
Limits
Test ConditionsMin. Typ. Max. Unit
l
CC
Supply Current (Active) 3 mA f
SCL
= 100kHz, SDA = Open, Other Inputs = V
SS
I
SB
V
CC
Current (Standby) 200 500 µA SCL = SDA = V
CC
, Addr. = V
SS
I
LI
Input Leakage Current 10 µA V
IN
= V
SS
to V
CC
I
LO
Output Leakage Current 10 µA V
OUT
= V
SS
to V
CC
V
IH
Input HIGH Voltage 2 V
CC
+ 1 V
V
IL
Input LOW Voltage -1 0.8 V
V
OL
Output LOW Voltage 0.4 V I
OL
= 3mA
Parameter Min. Unit
Minimum endurance 100,000 Data changes per bit per register
Data retention 100 years
Symbol Parameter Max. Unit Test Conditions
C
I/O
(5)
Input/output capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
(5)
Input capacitance (A0, A1, A2, A3 and SCL) 6 pF V
IN
= 0V
Symbol Parameter Min. Max. Unit
t
PUR
(6)
Power-up to initiation of read operation 1 ms
t
PUW
(6)
Power-up to initiation of write operation 5 ms
t
R
V
CC
V
CC
Power-up ramp rate 0.2 50 V/ms
X9221A
WAVEFORM INPUTS OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Dont Care:
Changes
Allowed
Changing:
State Not
Known
N/A Center Line
is High
Impedance
5V
1533Ω
100pF
SDA Output
R
H
C
H
10pF
C
W
R
L
C
L
R
W
R
TOTAL
25pF
10pF
Macro Model
120
100
80
40
60
20
20 40 60 80
100
120
0
0
Bus Capacitance (pF)
Min.
Resistance
Max.
Resistance
R
MAX
=
C
BUS
t
R
R
MIN
=
I
OL MIN
V
CC MAX
=1.8kΩ
Resistance (kΩ)
11
FN8163.2
August 30, 2006
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Equivalent A.C. Test Circuit
Circuit #3 SPICE Macro Model
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing levels V
CC
x 0.5
X9221A
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
t
LOW
t
F
t
SU:STO
t
R
t
BUF
SCL
SDA
(Data in)
t
AA
t
DH
SCL
SDA
SDA
OUT
(ACK) SDA
OUT
SDA
OUT
12
FN8163.2
August 30, 2006
TIMING DIAGRAMS
Figure 10. Input Bus Timing
Figure 11. Output Bus Timing
A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated)
Symbol Parameter
Limits
Unit
Reference
FigureMin. Max.
f
SCL
SCL clock frequency 0 100 kHz 10
t
LOW
Clock LOW period 4700 ns 10
t
HIGH
Clock HIGH period 4000 ns 10
t
R
SCL and SDA rise time 1000 ns 10
t
F
SCL and SDA fall time 300 ns 10
T
i
Noise suppression time constant (glitch filter) 100 ns 10
t
SU:STA
Start condition setup time (for a repeated start condition) 4700 ns 10 & 12
t
HD:STA
Start condition hold time 4000 ns 10 & 12
t
SU:DAT
Data in setup time 250 ns 10
t
HD:DAT
Data in hold time 0 ns 10
t
AA
SCL LOW to SDA data out valid 300 3500 ns 11
t
DH
Data out hold time 300 ns 11
t
SU:STO
Stop condition setup time 4700 ns 10 & 12
t
BUF
Bus free time prior to new transmission 4700 ns 10
t
WR
Write cycle time (nonvolatile write operation) 10 ms 13
t
STPWV
Wiper response time from stop generation 1000 µs 13
t
CLWV
Wiper response from SCL LOW 500 µs 6
X9221A

X9221AWSIZT1

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs 10K DL EEPOT TMPOT CMOS IND
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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