SCL from
Data Output
1
89
START
Acknowledge
Master
from Transmitter
Data Output
from Receiver
7
FN8163.2
August 30, 2006
Figure 7. Acknowledge Response from Receiver
DETAILED OPERATION
Both XDCP potentiometers share the serial interface
and share a common architecture. Each potentiometer
is comprised of a resistor array, a wiper counter regis-
ter and four data registers. A detailed discussion of the
register organization and array operation follows.
Wiper Counter Register
The X9221A contains two wiper counter registers
(WCR), one for each XDCP potentiometer. The WCR
can be envisioned as a 6-bit parallel and serial load
counter with its outputs decoded to select one of sixty-
four switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
directly by the host via the Write WCR instruction
(serial load); it may be written indirectly by transferring
the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it
can be modified one step at a time by the Increment/
Decrement instruction; finally, it is loaded with the con-
tents of its data register zero (R0) upon power-up.
The WCR is a volatile register; that is, its contents are
lost when the X9221A is powered-down. Although the
register is automatically loaded with the value in R0
upon power-up, it should be noted this may be differ-
ent from the value present at power-down.
Data Registers
Each potentiometer has four nonvolatile data regis-
ters. These can be read or written directly by the host
and data can be transferred between any of the four
data registers and the WCR. It should be noted all
operations changing data in one of these registers is a
nonvolatile operation and will take a maximum of
10ms.
If the application does not require storage of multiple
settings for the potentiometer, these registers can be
used as regular memory locations that could possibly
store system parameters or user preference data.
X9221A
