CPC7512ZTR Datasheet CPC7512Z, CPC7512ZTR | P10-P12

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3. Functional Description

3.1 Introduction

The CPC7512 Dual, 1Form-A, Shunt-Isolated

High-Voltage, High-Frequency, Analog Switch has two

symmetrical switch arrays with four operating states to

facilitate switching of high-frequency, high-voltage

signals using the AB and C switch states and the

flexibility to provide a variety of alternative switching

solutions for low-frequency high-voltage signal

applications. Operational states and logical behavior

of the device is shown in the “Truth Table” on

page 8. Switch organization consists of two channels,

each having three switches.

Within each channel there is an independent LATCH

input and a common Thermal Shutdown circuit that is

shared by the two channels. Other than the shared

TSD circuit, switch functionality under normal

operating conditions within each channel is

independent of the other channel. In designs where

the switches will be required to carry high load

currents or operate in higher temperature

environments, the thermal specifications should be

reviewed because the TSD circuit is shared by both

channels. An excess thermal condition in one channel

resulting in an active TSD event will cause an

interruption in the other channel as well when the TSD

protection circuit activates.

Solid-state switch construction of the CPC7512 offers

clean, bounce-free switching with simple TTL logic

level input control to provide access to high voltage

interfaces without the impulse noise generated by

traditional electromechanical switching techniques.

TTL logic level input control eliminates the additional

driver circuitry required by traditional techniques.

The low on-resistance (R

) symmetrical linear

switches utilized in the AB switch state are configured

as matched pairs, SW1

/SW1

and SW2

/SW2

, for

improved performance when differential access is

required. Their symmetrical construction provides an

additional degree of design flexibility allowing either

side of the switch to be connected to the high voltage

network.

Integrated into the CPC7512 switches are high

frequency dynamic current limiting and thermal

shutdown mechanisms to provide protection for the

electronics being connected to a high voltage network

during a fault condition. High frequency positive and

negative transient currents such as lightning are

reduced by the dynamic current limiting function while

protection from prolonged low frequency power-cross

and DC currents is provided by the thermal shutdown

circuitry.

To protect against a high voltage fault in excess of the

CPC7512’s maximum voltage rating, use of an

over-voltage protector is required. The protector must

limit the voltage seen at the switch terminals to a level

less than the switches’ breakdown voltage. To

minimize the stress on the solid-state contacts, use of

a foldback or crowbar type protector is highly

recommended. With proper selection of the protector,

telecom applications using the CPC7512 will meet all

relevant ITU, LSSGR, TIA/EIA and IEC protection

requirements.

Operating from a single +5V supply the CPC7512 has

extremely low power consumption.

3.2 Under-Voltage Switch Lock-Out Circuitry

Smart logic in the CPC7512 provides for switch state

control during both power up and power loss

transients to prevent undesired connections to high

voltage networks. This is done by setting the switches’

logic to the All-Off state. An internal detector evaluates

the V

supply against internally set thresholds to

determine when to de-assert the under-voltage switch

lock-out circuitry with a rising V

, and when to assert

the under-voltage switch lock-out circuitry with a falling

. Any time unsatisfactory low V

conditions exist,

the lock-out circuit overrides user switch control by

blocking the external information applied to the input

pins, output by the internal latch, and conditioning the

internal switch commands to the All-Off state. Upon

restoration of V

, the switches will remain off until the

LATCH

input is pulled low at which time proper

conditioning of the Sx

IN0

and Sx

IN1

inputs must be

made.

The rising V

lock-out release threshold ensures all

internal logic is properly biased and functional before

accepting external switch commands from the inputs.

For a falling V

event, the lock-out threshold is set to

assure proper logic and switch behavior up to the

moment the switches are forced off and external

inputs are suppressed.

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3.3 Switch Logic

The CPC7512 under-voltage switch lock-out circuitry

monitors the V

supply to ensure proper and safe

switch behavior whenever the supply voltage is

inadequate.

Under normal V

supply conditions data applied to

the Sx

IN0

and Sx

IN1

inputs is controlled by the LATCH.

The LATCH, depending on the logic level applied to it’s

control input LATCH

, will either block the input data or

pass the input data to the switch control logic. Once

the input data is passed to the switch control logic, the

value from the inputs will be locked by the LATCH

when the LATCH

control is asserted to a logic HIGH.

3.3.1 Data Latch

The CPC7512 has two integrated transparent data

latches, one for each channel. The latch-enable

operation is controlled by TTL input logic levels at the

LATCH

pins. Inputs to the data latch are via the Sx

IN0

and Sx

IN1

input pins while the data latch outputs are

internal nodes used for state control. When LATCH

the latch enable control pin, is at a logic 0 the data

latch is transparent and the input control signals flow

directly through the data latch to the state control

circuitry. A change in input will be reflected by a

change in the switch state.

Whenever the latch enable control pin is at logic 1, the

data latch is active and the control data is locked.

Subsequent changes to the Sx

input control pins will

not result in a change to the control logic or affect the

existing switch states.

The switches will remain in the state they were in

when the LATCH

changes from logic 0 to logic 1, and

will not respond to subsequent changes in input as

long as the LATCH

is at logic 1. TSD however is not

constrained by the latch function. Since internal

thermal shutdown control is not affected by the state of

the latch enable input, TSD will override state control.

3.3.2 TSD Pin Description

The TSD pin is a bidirectional I/O structure with an

internal pull-up resistor sourced from V

. As an

output, this pin indicates the status of the thermal

shutdown circuitry of the CPC7512. During normal

operation this pin will typically be pulled up to V

but

under fault conditions that create excess thermal

loading, the entire device will enter thermal shutdown

and a logic low will be output at TSD.

As an input, the TSD pin can be used to place the

device into the All-Off state by simply pulling the input

low. This is a convenient way to temporarily place the

device’s switches into the off state without the need to

cycle the inputs and LATCH controls through an off

and then an on sequence. When TSD is released, the

device will revert back to it’s previous state.

When using TSD as an input, IXYS Integrated Circuits

Division recommends the use of an open-collector or

an open-drain type output to apply the logic LOW.

Forcing TSD to a logic 1 or tying it to V

does not

affect the CPC7512 thermal shutdown functionality.

The device ignores this input level and still enters the

thermal shutdown state at high temperature. In other

words, the thermal shutdown feature can not be

overridden by an external pull-up on the TSD control.

3.4 Power Supplies

Only a +5V logic supply and ground are required by

the CPC7512. Switch state control is powered

exclusively by the +5V supply. As a result, the

CPC7512 exhibits extremely low power consumption

during active and idle states.

3.5 Protection

The CPC7512 provides protection for both the low

voltage side circuitry it connects to high voltage

networks and itself. Two separate layers of protection

are interleaved within the device to protect against

high-energy high-frequency transients and

high-power, low-frequency fault conditions.

3.5.1 Dynamic High Frequency Current Limit

While in a closed switch state, high-frequency

high-energy current is restricted by the CPC7512. For

the telecom GR-1089-CORE specified +

1000V

10x1000s lightning pulse with a generator source

impedance of 10 applied to the high voltage network

though a properly clamped external protector, the

current seen at the CPC7512 low voltage side

interface will be a pulse with a typical magnitude of 1A

and a duration less than 0.5s.

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3.5.2 Thermal Shutdown

The thermal-shutdown mechanism activates when the

device’s die temperature reaches a minimum of

110°C, placing the device into the All-Off state

regardless of logic input. During thermal shutdown

events the TSD pin will output a logic low with a

nominal 0V level. A logic high is output from the TSD

pin during normal operation with a typical output level

equal to V

If presented with a short-duration transient, such as a

lightning event, the thermal-shutdown feature will

typically not activate. But, in an extended power-cross

event the device temperature will rise and the thermal

shutdown mechanism will activate, forcing the device’s

switches to the All-Off state. At this point the current

into the active switch will drop to zero. Once the device

enters thermal shutdown, it will remain in the All-Off

state until the internal temperature of the device drops

below the de-activation level of the thermal-shutdown

circuit. This permits the circuit to autonomously return

to normal operation. If the fault has not passed,

current will again flow and heating will resume,

causing the thermal-shutdown mechanism to

reactivate. This cycle of entering and exiting the

thermal-shutdown mode will continue as long as the

fault condition persists. If the magnitude of the fault

condition is great enough, with an external

over-voltage protector present, the external protector

will activate shunting the fault current to ground.

3.6 External Protection Elements

The CPC7512 requires only over-voltage protection

on the high-voltage side of the switch. Additional

external protection may be required on the low-voltage

side of the switch if the threshold of the high-voltage

side protector exceeds the safe operation of the

low-voltage side components. Because the fault

current seen by the low-voltage side protector is

limited by the switch’s high frequency dynamic current

limit, the low-voltage side protector need not be as

capable as that of the high-voltage side protector. The

high-voltage side protector must limit voltage

transients to levels that do not exceed the breakdown

voltage or input-output isolation barrier of the

CPC7512. A foldback or crowbar type protector on the

high-voltage side is recommended to minimize

stresses on the CPC7512.

3.7 Thermal Design Assessment

A successful design utilizing the CPC7512

High-Voltage Analog Switch Array is dependent on

careful consideration of the application’s environment

and the device’s thermal constraints. For matters

regarding the electrical design, this is simply a case of

following the parameters provided in the preceding

tables and for many this will be sufficient. However,

those designers wishing to push the operational limits

envelope with higher switch current and/or higher

ambient operating temperatures will need to consider

the thermal performance.

Being a real physical device the CPC7512 has a finite

thermal capability that when properly considered will

ensure appropriate behavior and performance.

Determination of the thermal constraint is easily

accomplished using the following power equations:

and

Where is the dissipated power drawn from the

supply and is the total power dissipated by

all active switches. The V

power can be calculated

from the “VDD Voltage Supply Specifications” on

page 7 while the power dissipated by the switches is

the sum of the concurrently active switches. Total

switch power is the sum of: the squared maximum

current through each active switch times the

On-Resistance of the switch (I

SWx

The second equation is used to calculate the

maximum ambient temperature the device can be

operated in based on the calculated total power of the

previous equation. P

TOTAL

, the value obtained in the

first equation; T, the junction temperature rise of the

CPC7512 from ambient; and 

, the thermal

impedance of the device package are used to

determine the maximum operating ambient

temperature.

TOTAL

P

TOTAL

T



---------=

P

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

CPC7512ZTR

Mfr. #:

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Switch ICs - Various Dual 1-Form-A High V, Isolated Switch

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