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CPC7512ZTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC7512
R01 www.ixysic.com 7
1.8 V
DD
Voltage Supply Specifications
Note: To ensure compliance of the “No Overlap” parameter given in Section 1.7 "Switch Timing Specifications” on
page 6, the operational voltage range is reduced as listed above.
1.9 Protection Circuitry Thermal Specifications
Parameter Test Conditions Symbol Minimum Typical Maximum Unit
Voltage Requirements
Voltage operational range
-
V
DD
4.5 5 5.5 V
No Overlap: See Note
V
DD
4.7555.25V
Current Specifications
V
DD
Current 4.5 < V
DD
< 5.5V, All States,
All logic I/O = Open
I
DD
0.4 1.5 2.3 mA
Under Voltage Lockout Specifications
Thresholds V
DD
rising
UVLO
-3.4-
VV
DD
falling
-3-
Hysteresis - 0.4 -
Parameter Conditions Symbol Minimum Typical Maximum Unit
Thermal Shutdown Temperature Specifications
1
Thermal shutdown activation
temperature
Not production tested - limits are guaranteed by
design and Quality Control sampling audits
T
TSD_on
110 125 150 C
Shutdown circuit hysteresis
T
TSD_off
10 - 25 C
1
Thermal shutdown flag (TSD) will be high during normal operation and low during thermal shutdown state.
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC7512
8 www.ixysic.com R01
1.10 Truth Table
The truth table and block diagram are shown for Switch 1. Operation is the same for both switches, S1 and S2. Refer
to accompanying block diagram.
LATCH
1
S1
IN1
S1
IN0
TSD
SW1
A
SW1
B
SW1
C
Switch State
000
Z
2
OFF OFF OFF
All-Off: All switches are open (Off)
1
001
OFF ON ON
BC: S1
B
connected to S1
C
010 ON ON OFF
AB: S1
A
connected to S1
B
011
OFF OFF ON
C: S1
C
connected S1
COM
1xx
Unchanged Unchanged Unchanged Latest switch state persists
xxx
0
3
OFF OFF OFF
Thermal shutdown active,
all switches are open (Off)
xxx
0
4,5
OFF OFF OFF All-Off: All switches are open (Off)
1
Default state following power up and after an under-voltage lock out event.
2
Z = High Impedance with a weak internal pull-up. Because TSD has an internal pull-up, it should be controlled with an open-collector or open-drain type device.
3
TSD outputs a logic low.
4
TSD driven to a logic low by an external device. External device output should be an open-collector or an open-drain type.
5
When TSD is released, the switches revert back to their previous state.
S1
B
S1
C
S1
COM
S1
A
LATCH
1
S1
IN0
S1
IN1
Switch 1
Control
Logic
L
A
T
C
H
TSD
SW1
A
SW1
B
SW1
C
I
NTEGRATED
C
IRCUITS
D
IVISION
CPC7512
R01 www.ixysic.com 9
2. Performance Data
Figure 3. On-State Insertion Loss: Sx
A
to Sx
B
Figure 4. Off-State Switch Isolation: Sx
A
to Sx
B
Figure 5. Switch to Switch Cross Talk
V
M
+
V
S
50Ω
+20 log
V
S
V
M
Insertion Loss =
AB
C
Frequency
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz 1GHz
Loss (dB)
10
8
6
4
2
0
Insertion Loss Into 50Ω
Frequency
Isolation (dB)
140
120
100
80
60
40
20
0
Off-State Isolation into 50Ω
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz
Isolation =
+20 log
V
S
V
M
V
M
+
V
S
50Ω
AB
C
Frequency
1kHz 10kHz 100kHz 1MHz 10MHz 100MHz
Transfer Gain (dB)
-140
-120
-100
-80
-60
-40
-20
0
Cross Talk into 50Ω
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CPC7512ZTR

Mfr. #:
Buy CPC7512ZTR
Manufacturer:
IXYS Integrated Circuits
Description:
Switch ICs - Various Dual 1-Form-A High V, Isolated Switch
Lifecycle:
New from this manufacturer.
Delivery:
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