Features
Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third-party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera
®
FLEX
®
, APEX
Devices,
Lucent
®
ORCA
®
FPGAs, Xilinx
®
XC3000, XC4000, XC5200, Spartan
®
, Virtex
®
FPGAs,
Motorola
®
MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Footprint Packages), 20-lead PLCC and 44-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 10,000 Write Cycles Typical
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators)
provide an easy-to-use, cost-effective configuration memory for Field Programmable
Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC
and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple
serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1. AT17F Series Packages
Package AT17F16
8-lead LAP Yes
20-lead PLCC Yes
44-lead TQFP Yes
FPGA
Configuration
Flash Memory
AT17F16
3392F–CNFG–2/08
2
3392F–CNFG–2/08
AT17F16
2. Pin Configuration
8-lead LAP
20-lead PLCC
44 TQFP
8
7
6
5
1
2
3
4
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
4
5
6
7
8
18
17
16
15
14
CLK
NC
RESET/OE
PAGESEL1
CE
NC
SER_EN
PAGE_EN
READY
CEO (A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
PAGESEL0
NC
NC
NC
DATA
NC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
PAGESEL0
CE
NC
NC
GND
PAGESEL1
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
PAGE_EN
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
3
3392F–CNFG–2/08
AT17F16
3. Block Diagram
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration device without requiring an external
intelligent controller.
The RESET
/OE and CE pins control the tri-state buffer on the DATA output pin and enable the
address counter. When RESET/OE is driven Low, the configuration device resets its address
counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17F Series
Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA
output pin are enabled. When RESET
/OE is driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO
is driven Low, the device tri-states
the DATA pin to avoid contention with other configurators. Upon power-up, the address counter
is automatically reset.
Config. Page
Select
Power-on
Reset
Flash
Memory
Clock/Oscillator
Logic
2-wire Serial Programming
Serial Download Logic
Control Logic
CLK
CEO(A2)
DATA
CE
RESET/OE
SER_EN
CE/WE/OE
Data
Address
READY
PAGE_EN
PAGESEL0
PAGESEL1
Reset

AT17F16-30CU

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
FPGA - Configuration Memory SERIAL CONFIG FLASH 16M - 30MHZ 8 LAP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union