NXP Semiconductors
PSMN1R0-30YLC
N-channel 30 V 1.15 mΩ logic level MOSFET in LFPAK using
NextPower technology
PSMN1R0-30YLC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved
Product data sheet 15 January 2015 6 / 14
Symbol Parameter Conditions Min Typ Max Unit
R
G
gate resistance f = 1 MHz - 1.1 2.2 Ω
Dynamic characteristics
I
D
= 25 A; V
DS
= 15 V; V
GS
= 10 V;
Fig. 14; Fig. 15
- 103.5 145 nC
I
D
= 25 A; V
DS
= 15 V; V
GS
= 4.5 V;
Fig. 15; Fig. 14
- 50 70 nC
Q
G(tot)
total gate charge
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V; Fig. 15 - 96.5 - nC
Q
GS
gate-source charge - 12.9 - nC
Q
GS(th)
pre-threshold gate-
source charge
- 10.1 - nC
Q
GS(th-pl)
post-threshold gate-
source charge
- 2.8 - nC
Q
GD
gate-drain charge
I
D
= 25 A; V
DS
= 15 V; V
GS
= 4.5 V;
Fig. 14; Fig. 15
- 14.6 26 nC
V
GS(pl)
gate-source plateau
voltage
I
D
= 25 A; V
DS
= 15 V; Fig. 14 - 2.2 - V
C
iss
input capacitance 3322 6645 9968 pF
C
oss
output capacitance 605 1210 1815 pF
C
rss
reverse transfer
capacitance
V
DS
= 15 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; Fig. 16
240 481 842 pF
t
d(on)
turn-on delay time - 44 - ns
t
r
rise time - 77 - ns
t
d(off)
turn-off delay time - 108 - ns
t
f
fall time
V
DS
= 15 V; R
L
= 0.6 Ω; V
GS
= 4.5 V;
R
G(ext)
= 4.7 Ω
- 60 - ns
Q
oss
output charge V
GS
= 0 V; V
DS
= 15 V; f = 1 MHz;
T
j
= 25 °C
- 35.2 - nC
Source-drain diode
V
SD
source-drain voltage I
S
= 25 A; V
GS
= 0 V; T
j
= 25 °C; Fig. 17 - 0.8 1.1 V
t
rr
reverse recovery time - 45 - ns
Q
r
recovered charge
I
S
= 25 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 15 V
- 67 - nC
t
a
reverse recovery rise
time
- 28.5 - ns
t
b
reverse recovery fall
time
I
S
= 25 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 15 V; Fig. 18
- 16.5 - ns