X96010V14I Datasheet X96010V14IZ, X96010V14I | P13-P15

FN8214.1

October 25, 2005

L2DAS: LUT2 DIRECT ACCESS SELECT BIT (NON-

VOLATILE)

When bit L2DAS is set to “0” (default), LUT2 is

addressed by the output of the on-chip A/D converter.

When bit L2DAS is set to “1”, LUT2 is addressed by

bits L2DA5 - L2DA0.

D2DAS: D/A 2 D

IRECT ACCESS SELECT BIT (NON-

VOLATILE)

When bit D2DAS is set to “0” (default), the input to the

D/A converter 2 is a row of LUT2. When bit D2DAS is set

to “1”, that input is the content of the Control register 4.

Control Register 6

This register is accessed by performing a Read or

Write operation to address 86h of memory.

WEL: W

RITE ENABLE LATCH (VOLATILE)

The WEL bit controls the Write Enable status of the

entire X96010 device. This bit must be set to “1” before

any other Write operation (volatile or nonvolatile). Oth-

erwise, any proceeding Write operation to memory is

aborted and no ACK is issued after a Data Byte.

The WEL bit is a volatile latch that powers up in the “0”

state (disabled). The WEL bit is enabled by writing

10000000

to Control register 6. Once enabled, the

WEL bit remains set to “1” until the X96010 is powered

down, and then up again, or until it is reset to “0” by

writing 00000000

to Control register 6.

A Write operation that modifies the value of the WEL bit

will not cause a change in other bits of Control register 6.

Status Register - ADC Output

This register is accessed by performing a Read opera-

tion to address 87h of memory.

AD7 - AD0: A/D C

ONVERTER OUTPUT BITS (READ

ONLY)

These eight bits are the binary output of the on-chip

A/D converter. The output is 00000000

for minimum

input and 11111111

for full scale input. The six MSBs

select a row of the LUTs.

X96010

FN8214.1

October 25, 2005

VOLTAGE REFERENCE

The voltage reference to the A/D and D/A converters

on the X96010, may be driven from the on-chip volt-

age reference, or from an external source via the VRef

pin. Bit VRM in Control Register 0 selects between the

two options (See Figure 5).

The default value of VRM is “0”, which selects the

internal reference. When the internal reference is

selected, it’s output voltage is also an output at pin

VRef with a nominal value of 1.21 V. If an external volt-

age reference is preferred, the VRM bit of the Control

Figure 5. Voltage Reference Structure

A/D CONVERTER

The X96010 contains a general purpose, on-chip, 8-bit

Analog to Digital (A/D) converter whose output is avail-

able at the Status Register as bits AD[7:0]. By default

these output bits are used to select a row in the look-

up tables associated with the X96010’s Current Gen-

erators. When bit ADCfiltOff is “0” (default), bits

AD[7:0] are updated each time the ADC performs four

consecutive conversions with the same exact result at

the 6 MSBs. When bit ADCfiltOff is “1”, these bits are

updated after every ADC conversion.

A block diagram of the A/D converter is shown in Fig-

ure 6. The voltage reference input (see “VOLTAGE

REFERENCE” for details), sets the maximum ampli-

tude of the ramp generator output. The A/D converter

input signal (see “A/D Converter Input Select” below

for details) is compared to the ramp generator output.

The control and encode logic produces a binary

encoded output, with a minimum value of 00h (0

and a full scale output value of FFh (255

The A/D converter input voltage range (VIN

ADC

) is

from 0 V to V(VRef).

VRM: bit 2 in Control register 0.

VRef Pin

On-chip

A/D Converter and

Voltage

Reference

D/A Converters reference

Figure 6. A/D Converter Block Diagram

Ramp

Generator

VSense Pin

From VRef

Clock

Control and

Encode Logic

Conversion Reset

A/D Converter

Output

(To LUTs and

Status Register)

Comparator

X96010

FN8214.1

October 25, 2005

A/D Converter Range

From Figure 6 we can see that the operating range of the

A/D converter input depends on the voltage reference.

The table below summarizes the voltage range

restrictions on the VSense and VRef pins in different

configurations :

VSense and VRef ranges

LOOK-UP TABLES

The X96010 memory array contains two 64-byte look-

up tables. One is associated to pin I1’s output current

generator and the other to pin I2’s output current gen-

erator, through their corresponding D/A converters.

The output of each look-up table is the byte contained

in the selected row. By default these bytes are the

inputs to the D/A converters driving pins I1 and I2.

The byte address of the selected row is obtained by

adding the look-up table base address (90h for LUT1,

and D0h for LUT2) and the appropriate row selection

bits. See Figure 8.

By default the look-up table selection bits are the

6 MSBs of the A/D converter output. Alternatively,

the A/D converter can be bypassed and the six row

selection bits are the six LSBs of Control Registers

1 and 2, for the LUT1 and LUT2 respectively. The

selection between these options is illustrated in Fig-

ure 9, and described in “I2DS: Current Generator 2

Direction Select Bit (Non-volatile)” on page 12, and

“Control Register 2” on page 12.

CURRENT GENERATOR BLOCK

The Current Generator pins I1 and I2 are outputs of

two independent current mode D/A converters.

D/A Converter Operation

The Block Diagram for each of the D/A converters is

shown in Figure 7.

The input byte of the D/A converter selects a voltage

on the non-inverting input of an operational amplifier.

The output of the amplifier drives the gate of a FET,

whose source is connected to ground via resistor R1

or R2. This node is also fed back to the inverting input

of the amplifier. The drain of the FET is connected to

the output current pin (I1 or I2) via a “polarity select”

circuit block.

VRef A/D Converter Input Ranges

Internal VSense Pin 0  V(VSense) 

V(VRef)

External VSense Pin 0 V(VRef)  1.3 V

0  V(VSense) 

V(VRef)

All voltages referred to Vss.

X96010

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

X96010V14I

Mfr. #:

Buy X96010V14I

Manufacturer:

Renesas / Intersil

Description:

IC SENSOR COND 2WIRE 14TSSOP

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X96010V14I

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