X96010V14I Datasheet X96010V14IZ, X96010V14I | P4-P6

FN8214.1

October 25, 2005

Notes: 1. The device goes into Standby: 200 ns after any STOP, except those that initiate a nonvolatile write cycle. It goes into Standby t

after

a STOP that initiates a nonvolatile write cycle. It also goes into Standby 9 clock cycles after any START that is not followed by the cor-

rect Slave Address Byte.

2. t

is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It

is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

3. For this range of V(VRef) the full scale sink mode current at I1 and I2 follows V(VRef) with a linearity error smaller than 1%.

4. This parameter is periodically sampled and not 100% tested.

5. TCO

ref

= [Max V(V

REF

) - Min V(V

REF

)] x 10

/(1.21V x 140°C)

IHCMOS

WP, A0, A1, and A2 input

High voltage

0.8 x

Vcc

Vcc V

VRefout Output Voltage at VRef at

25°C

1.205 1.21 1.215 V -20 A  I(VRef)  20 A

RVref VRef pin input resistance 20 40 k VRM bit = “1”, 25°C

TCOref Temperature coefficient of

VRef output voltage

-100 +100 ppm/°

See note 4 and 5.

VRef Range Voltage range when VRef

is an input

1 1.3 V See note 3.

Current from pin R1 or R2

to Vss

0 3200 A

POR

Power-on reset threshold

voltage

1.5 2.8 V

VccRamp Vcc Ramp Rate 0.2 50 mV /



ADCOK

ADC enable minimum

voltage

2.6 2.8 V See Figure 10.

ELECTRICAL CHARACTERISTICS (Continued) (Conditions are as follows, unless otherwise specified)

All typical values are for 25°C ambient temperature and 5V at pin Vcc. Maximum and minimum specifications are over

the recommended operating conditions. All voltages are referred to the voltage at pin Vss. Bit 3 in Control register 0 is

“1”, while all other bits in control registers are “0”. 255, 0.1%, resistor connected between R1 and Vss, and another

between R2 and Vss. 400kHz TTL input at SCL. SDA pulled to Vcc through an external 2k resistor. 2-wire interface

in “standby” (see notes 1 and 2 on page 5). WP

, A0, A1, and A2 floating. VRef pin unloaded.

Symbol Parameter Min Typ Max Unit Test Conditions / Notes

X96010

FN8214.1

October 25, 2005

D/A CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)

Notes: 1. DAC input Byte = FFh, Source or sink mode.

2. LSB is defined as divided by the resistance between R1 or R2 to Vss.

3. Offset

DAC

: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is

expressed in LSB.

FSError

DAC

: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It

is expressed in LSB. The Offset

DAC

is subtracted from the measured value before calculating FSError

DAC

DNL

DAC

: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in

the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset

and Full Scale Error before calculating DNL

DAC

INL

DAC

: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjust-

ing the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB.

4. These parameters are periodically sampled and not 100% tested.

5. V(I1) and V(I2) are V

- 1.2V in source mode and 1.2V in sink mode. In this range the current at I1 or I2 varies <1%.

6. The maximum current, sink or source, can be set with an external resistor to 3.2 mA with a minimum V

= 4.5V. The compliance volt-

age changes to 2.5V from the sourcing rail, and the current variation is <1%.

Symbol Parameter Min Typ Max Unit Test Conditions / Notes

IFS I1 or I2 full scale current 1.56 1.58 1.6 mA See note 1, 5, R = 510

3.2 mA See note 1, 4, 6, R = 255

Offset

DAC

I1 or I2 D/A converter offset error 1 1 LSB See notes 2 and 3.

FSError

DAC

I1 or I2 D/A converter full scale error -2 2 LSB

DNL

DAC

I1 or I2 D/A converter

Differential Nonlinearity

-0.5 0.5 LSB

INL

DAC

I1 or I2 D/A converter Integral Nonlin-

earity with respect to a straight line

through 0 and the full scale value

-1 1 LSB

ISink

I1 or I2 Sink Voltage Compliance 1.2 Vcc V See note 5

2.5 Vcc V See note 4, 6

ISource

I1 or I2 Source Voltage Compliance 0 Vcc-1.2 V See note 5

0 Vcc-2.5 V See note 4, 6

OVER

I1 or I2 overshoot on D/A Converter

data byte transition

0 A DAC input byte changing from

00h to FFh and vice

versa, V(I1) and V(I2) are

Vcc - 1.2V in source mode

and 1.2V in sink mode.

See note 4.

UNDER

I1 or I2 undershoot on D/A Converter

data byte transition

0 A

rDAC

I1 or I2 rise time on D/A Converter data

byte transition; 10% to 90%

530s

TCO

Iout

Temperataure coefficient of output

current due to internal parameters

-100 +100 ppm/

°C

See Figure 7.

VRMbit = “0”

V(VRef)

255

[]

X96010

FN8214.1

October 25, 2005

A/D CONVERTER CHARACTERISTICS (See pg. 4 for Standard Conditions)

Notes: 1. “LSB” is defined as V(VRef)/255, “Full Scale” is defined as V(VRef).

2. Offset

ADC

: For an ideal converter, the first transition of its transfer curve occurs at above zero. Offset error is the

amount of deviation between the measured first transition point and the ideal point.

FSError

ADC

: For an ideal converter, the last transition of its transfer curve occurs at . Full Scale Error is the

amount of deviation between the measured last transition point and the ideal point,

after subtracting the Offset from the measured curve.

DNL

ADC

: DNL is defined as the difference between the ideal and the measured code transitions for successive A/D code outputs

expressed in LSBs. The measured transfer curve is adjusted for Offset and Fullscale errors before calculating DNL.

INL

ADC

: The deviation of the measured transfer function of an A/D converter from the ideal transfer function. The INL error is also

defined as the sum of the DNL errors starting from code 00h to the code where the INL measurement is desired. The measured trans-

fer curve is adjusted for Offset and Fullscale errors before calculating INL.

3. These parameters are periodically sampled and not 100% tested.

Symbol Parameter Min Typ Max Unit Test Conditions / Notes

ADCTIME A/D converter conversion

time

9 ms Proportional to A/D converter

input voltage. This value is

maximum at full scale input

of A/D converter.

ADCfiltOff = “1”

RIN

ADC

VSense pin input

resistance

100 k VSense as an input,

ADCIN bit = “1”

CIN

ADC

VSense pin input

capacitance

1 7 pF VSense as an input,

ADCIN bit = “1”,

Frequency = 1 MHz

See note 3.

VIN

ADC

VSense input signal range 0 V(VRef) V This is the A/D Converter

Dynamic Range. ADCIN bit = “1”

The ADC is monotonic

Offset

ADC

A/D converter offset error ±1 LSB See notes 1 and 2

FSError

ADC

A/D converter full scale error ±1 LSB

DNL

ADC

A/D Converter Differential

Nonlinearity

±0.5 LSB

INL

ADC

A/D converter Integral

Nonlinearity

±1 LSB

0.5 x V(VRef)

255

[]

254.5

x V(VRef)

255

[]

X96010

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

X96010V14I

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

IC SENSOR COND 2WIRE 14TSSOP

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X96010V14I

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