REVISION A 8/21/15
843201-375 DATA SHEET
13 FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the 843201-375.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 843201-375 is the sum of the core power plus the power dissipated due to loading.
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated due to loading.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 108mA = 374.2mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V) = 374.2mW + 30mW = 404.2mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming 0 air fl ow
and a multi-layer board, the appropriate value is 99.9°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.404W * 99.9°C/W = 110°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (multi-layer).
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 8. THERMAL RESISTANCE θ
JA
FOR 16-PIN TSSOP, FORCED CONVECTION
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 99.9°C/W 35.6°C/W 93.5°C/W
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
843201-375 DATA SHEET
14 REVISION A 8/21/15
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
To calculate power dissipation due to loading, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
REVISION A 8/21/15
843201-375 DATA SHEET
15 FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for 843201-375 is: 2433
TABLE 9. θ
JA
VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 99.9°C/W 35.6°C/W 93.5°C/W

843201AG-375LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 1 LVPECL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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