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MPC855TCVR66D4

P1-P3P4-P6P7-P9P10-P12P13-P15
The MPC855T communications controller is a member of the MPC8xx family targeted at cost
sensitive general purpose networking controller applications. The MPC855T can be used in a
variety of controller applications, excelling particularly in low cost communications and
networking products, such as SOHO routers, ADSL, and cable modems.
The MPC855T integrates three separate processing blocks. The first two, common with all
MPC8xx devices, are (1) a high-performance MPC8xx core, which is used as a
general-purpose processor for application programming and (2) a RISC communications
processor (CP) embedded in the communications processor module (CPM). All MPC8xx
devices will have an 8-KByte dual port RAM when the MPC855T is available. The third block
is a 10/100-Mbps Fast Ethernet controller with integrated FIFOs and bursting DMA. The
MPC855T’s Fast Ethernet controller is implemented independently, providing
high-performance Fast Ethernet connectivity without affecting the performance of the CPM.
Additionally, since the CPM of the MPC855T is based on the CPM of other MPC8xx devices,
support for ATM, HDLC, and the QMC (QUICC multichannel controller) multichannel
protocol is also provided. The QMC protocol enables the MPC855T to provide protocol
processing (through HDLC or transparent mode) for 32 time-division-multiplexed channels
(on TDM channel A) when the MPC855T is operated at 50 MHz. This support for
multichannel protocol processing, ATM and 10/100-Mbps Ethernet in one chip makes the
MPC855T ideal for cost sensitive networking and telecommunications systems.
1.1 MPC855T Key Features
The key features of the MPC855T are summarized as follows:
• 10/100-Mbps Ethernet support (Not available when using ATM over UTOPIA
interface)
— Full compliance with the IEEE 802.3u standard for 10/100-Mbps
— Support for three different physical interfaces
– 100-Mbps 802.3 media-independent interface (MII)
– 10-Mbps 802.3 media-independent interface
– 10-Mbps 7-wire interface
— Support for half-duplex 100-Mbps operation (at 33-MHz system clock rate and
above)
— Support for full-duplex 100-Mbps operation (at 50-MHz system clock rate and
Advance Information
MPC855TTS/D
Rev. 0.1, 11/2001
MPC855T Communications
Controller Technical
Summary
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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2 MPC855T Communications Controller Technical Summary MOTOROLA
MPC855T Key Features
above)
— Large on-chip transmit and receive FIFOs to support a variety of bus latencies
— Retransmission from transmit FIFO following a collision
— Automatic internal flushing of the receive FIFO for runts and collisions
— Off-chip buffer descriptor rings of user-definable size that allow nearly unlimited flexibility in
management of transmit and receive buffer memory
• 10/100-Mbps media access control (MAC) features
— Address recognition
– Broadcast
– Single station address
– Promiscuous mode
– Multicast hashing
— Full support of the media-independent interface
— Interrupt modes
– Per-frame
– Per-buffer (selectable buffer interrupt functionality using the I bit is not supported)
— Automatic interrupt vector generation for receive and transmit events
Categories: transmit interrupt, receive interrupt, non-time critical interrupt
— Ethernet channel bursts data to/from external memory
• ATM support
— Compliant with ATM forum UNI 4.0 specification
— Cell processing up to 50–70 Mbps at 50-MHz system clock
— Cell multiplexing/demultiplexing
— Support of AAL5 and AAL0 protocols on a per-VC basis
– AAL0 support enables OAM and software implementation of other protocols)
— ATM pace control (APC) scheduler, providing:
– Direct support of constant bit rate (CBR)
– Direct support of unspecified bit rate (UBR)
– Control mechanisms enabling software support of available bit rate (ABR)
— Support for two types of physical interfaces
– UTOPIA (10/100-Mbps is not supported with this interface)
– Byte-aligned serial (e.g. T1/E1/ADSL)
— UTOPIA-mode ATM supports:
– UTOPIA level 1 master with cell-level handshake
– Multi-PHY (up to 4 physical layer devices)
– Connection to 25 Mbps, 51 Mbps, or 155 Mbps framers
– UTOPIA clock rates of 1:2 or 1:3 system clock rates
— Serial-mode ATM connection supports:
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
MOTOROLA MPC855T Communications Controller Technical Summary 3
MPC855T Key Features
– Transmission convergence (TC) function for T1/E1/ADSL lines
– Cell delineation
– Cell payload scrambling/descrambling
– Automatic idle/unassigned cell insertion/stripping
– Header error control (HEC) generation, checking, and statistics
– Glueless interface to Motorola CopperGold ADSL transceiver
— Receive VP/VC connection lookup mechanisms, including:
– Internal sequential lookup table supporting up to 32 connections
– Support for up to 64K connections using external memory via address compression or
content-addressable memory (CAM)
— Independent transmit/receive buffer descriptor ring data structures for each connection
— Interrupt report per channel using exception queue
— Supports 53-byte or up to 64-byte (expanded) ATM cells
— AAL5 segmentation and reassembly (SAR) features for segmentation
– Segment CPCS_PDU directly from system memory
– CPCS_PDU padding
– CRC32 generation
– Automatic last cell marking (in PTI field of cell header)
– Automatic CS_UU, CPI, and LENGTH insertion in last cell
— AAL5 segmentation and reassembly (SAR) features for reassembly:
– Reassembles CPCS_PDU directly into system memory
– Removes CPCS_PDU padding
– CRC32 checking
– CS_UU, CPI, and LENGTH reporting
– CLP and congestion reporting
– Interrupts per buffer or per message
– Error reporting, including CRC, length mismatch, message abort
— AAL0 features for transmit include the following:
– Transmits user-defined cell from transmit emory buffer
– Automatic HEC generation
– Optional CRC10 insertion
— AAL0 features for receive include the following:
– Copies entire cell into receive memory buffer
– Provides interrupt per cell
– Optional CRC10 checking
• Embedded MPC8xx core with 106 MIPS at 80 MHz (using Dhrystone 2.1)
— Single-issue, 32-bit version of the embedded MPC8xx core (fully compatible with the
PowerPC user instruction set architecture; refer to the Programming Environments Manual for
32-Bit Implementations of the PowerPC Architecture for more information) with 32- x 32-bit
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
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MPC855TCVR66D4

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Manufacturer:
NXP / Freescale
Description:
Microprocessors - MPU POWER QUICC-NO LEAD
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