4 MPC855T Communications Controller Technical Summary MOTOROLA
MPC855T Key Features
fixed-point registers
– Embedded MPC8xx core performs branch folding and branch prediction with conditional
prefetch, but without conditional execution
– 4-Kbyte data cache and 4-Kbyte instruction cache, each with an MMU
– Instruction and data caches are two-way, set associative, physical address, 4-word line
burst, least recently used (LRU) replacement, lockable on cache line granularity
– MMUs with 32-entry, fully-associative instruction and data TLBs
– MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 256 Kbytes, 512 Kbytes, and
8 Kbytes; 16 virtual address spaces and 8 protection groups
– Advanced on-chip-emulation debug mode
— Up to 32-bit data bus (dynamic bus sizing of 8, 16, and 32 bits provided through memory
controller)
— 32 address lines
• System integration unit (SIU)
— Bus monitor
— Spurious interrupt monitor
— Software watchdog
— Periodic interrupt timer
— Low-power stop mode
— Clock synthesizer
— Decrementer
— Time base and RTC
— Reset controller
— IEEE 1149.1 test access port (JTAG)
— Memory controller (eight bank)
– Contains complete dynamic random-access memory (DRAM) controller
– Each bank may be a chip select or RAS to support a DRAM bank
– Up to 15 wait states programmable per memory bank
– Glueless interface to DRAM single in-line memory modules (SIMMs), static
random-access memory (SRAM), electrically programmable read-only memory
(EPROM), Flash EPROM, etc.
– DRAM controller programmable to support most size and speed memory interfaces
– Four CAS lines, four WE lines, one OE line
– Boot chip select available at reset (options for 8-, 16-, or 32-bit memory)
– Variable block sizes, 32 Kbytes to 256 Mbytes
– Selectable write protection
– On-chip bus arbitration logic
— General-purpose timers
– Four 16-bit timers or two 32-bit timers
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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