MAX5360/MAX5361/MAX5362
condition (Figure 6). The bus is then free for another
transmission.
SDA’s state is sampled, and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5360/MAX5361/MAX5362. Release SDA during
the 9th clock cycle as the selected device acknowl-
edges the receipt of the byte, by pulling SDA low dur-
ing this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
Slave Address
The MAX5360/MAX5361/MAX5362 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7 most
significant bits (MSBs) sent by the master after a
START condition. The address options are 0x60, 0x62,
0x64, and 0x66 (left justified with LSB set to 0). The 8th
bit, typically used to define a write or read protocol,
sets the device’s power mode (SHDN); the device is
powered down when SHDN is set to 1. During a device
search routine, the MAX5360/MAX5361/MAX5362
acknowledge both options (SHDN = 0 or SHDN = 1)
but does not change its power state if a stop condition
(or restart) is issued immediately. The second byte
(DAC data) must be sent/received for the device to
update both power mode and DAC output.
DAC Data
The 6-bit DAC data is decoded as straight binary MSB
first with 1LSB = (V
REF
/ 64) and converted into the cor-
responding analog voltage as shown in Table 1. Two
subbits complete the data byte; these 2 bits should be
set to zero since they are not tested to guaranteed-
monotonic performance.
After receiving the data byte, the MAX5360/MAX5361/
MAX5362 acknowledge its receipt and expect a STOP
condition, at which point the DAC output is updated.
The devices update the output and the power mode
only if the second byte is clocked in (SHDN = 0) or out
(SHDN = 1) of the device. When SHDN = 1, the master
will read all ones when clocking out a data byte. The
MAX5360/MAX5361/MAX5362 do not drive SDA except
for the acknowledge bit.
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
10 ______________________________________________________________________________________
SCL
SDA
START
CONDITION
STOP
CONDITION
1
32
4
65
7
98
10
1211
13
1514
16
1817
ACK
LSBMSBLSBMSB
0
11
0
X0
X
ACKSHDN
D6
D3D4
D2
D0D1
S1
S0
SLAVE ADDRESS BYTE DAC CODE
Figure 6. Complete Serial Transmission
SCL
SDA
START CONDITION
STOP CONDITION
Figure 5. Start and Stop Conditions
I
2
C Compatibility
The MAX5360/MAX5361/MAX5362 are compatible with
existing I
2
C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I
2
C application. The communication protocol
supports the standard I
2
C 8-bit communications. The
general call address is ignored, and CBUS formats are
not supported. The MAX5360/MAX5361/MAX5362
address is compatible with the 7-bit I
2
C addressing
protocol only. No 10-bit formats are supported.
RESTART protocol is supported, but an immediate
STOP condition is necessary to update the DAC.
Applications Information
Digital Inputs and Interface Logic
The serial 2-wire interface has logic levels defined as
V
OL
= 0.3 x V
DD
and V
OH
= 0.7 x V
DD
. All of the inputs
include Schmitt-trigger buffers to accept slow-transition
interfaces. This means that optocouplers can interface
directly to the MAX5360/MAX5361/MAX5362 without
additional external logic. The digital inputs are compati-
ble with CMOS logic levels and must not be driven with
voltages higher than V
DD
.
Power-Supply Bypassing and Layout
Careful PC board layout is important for best system
performance. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Ensure that
the ground return from GND to the supply ground is
short and low impedance; a ground plane is recom-
mended. Bypass V
DD
with a 0.1µF to ground as close
as possible to the device. If the supply is excessively
noisy, connect a 10Ω resistor in series with the supply
and V
DD
, and add additional capacitance
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
______________________________________________________________________________________ 11
μC
SDA SCL
V
DD
OFFSET ADJUSTMENT
THRESHOLD ADJUSTMENT
GAIN ADJUSTMENT
SCL
SDA
V
DD
OUT
MAX5360L
2V REFERENCE
SCL
SDA
V
DD
OUT
MAX5361M
4V REFERENCE
SCL
SDA
V
DD
OUT
MAX5362P
V
DD
REFERENCE
Figure 7. I
2
C Typical Application
PROCESS: BiCMOS
Chip Information
MAX5360/MAX5361/MAX5362
Low-Cost, Low-Power 6-Bit DACs with
2-Wire Serial Interface in SOT23 Package
12 ______________________________________________________________________________________
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO.
LAND
PATTERN NO.
5 SOT23 U5+1
21-0057
90-0174

MAX5360MEUK+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 6-Bit Precision DAC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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