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AD1953YSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
AD1953
–21–
Control Register 1
Control Register 1 is a 14-bit register that controls data capture
modes, serial modes, de-emphasis, mute, power-down, and
SPI-to-memory transfers. Table III documents the contents of
this register. Table IV details the two bits in the register’s
read operation.
Bits <1:0> set the wordlength, which is used in right-justified
serial modes to determine where the MSB is located relative to
the start of the audio frame.
Bits <3:2> select one of four serial modes, which are discussed
in the Serial Data Input Port section.
The de-emphasis curve selection Bits <5:4> turn on the internal
de-emphasis filter for one of three possible sample rates.
Bit <6>, the soft power-down bit, stops the internal clocks to
the DSP core, but does not reset the part. The digital power
consumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Soft mute (Bit <7>) is used to initiate a volume ramp-down
sequence. If the initial volume was set to 1.0, this operation will
take 512 audio frames to complete. When this bit is deasserted,
a ramp-up sequence is initiated until the volume returns to its
original setting.
The initiate-safe-transfer Bit <9> will request a data transfer
from the SPI safeload registers to the parameter RAM. The
safeload registers contain address-data pairs, and only those
registers that have been written to since the last transfer opera-
tion will be uploaded. The user may poll for this operation being
complete by reading Bit <0> of Control Register 1. The Safeload
Mechanism section goes into more detail on this feature.
Bit <10>, the halt program bit, is used to initiate a volume
ramp-down followed by a shutdown of the DSP core. The user
may poll for this operation being complete by reading Bit <1>
of Control Register 1.
The Data Capture Serial Out mode is controlled with Bits
<13:12>. This function can be used to send data that is cap-
tured using the data-capture feature to external devices such as
an external stereo DAC or multichannel codec. The Data Cap-
ture Registers and Outputs section gives more information about
the TDM and data capture features.
Table III. Control Register 1 Write Definition
Register Bits Function
13:12 Data Capture Serial Out Mode Control
00 = none
01 = TDM 6-channel out, uses Pins 41–43
10 = 2-channel out, uses Pin 45
11 = Unused
11 Unused
10 Halt Program (1 = Halt)
9 Initiate Safe Transfer (1 = Transfer)
8 Unused
7 Soft Mute (1 = Start Mute Sequence)
6 Soft Power-Down (1 = Power Down)
5:4 De-emphasis Curve Select
00 = none
01 = 44.1 kHz
10 = 32 kHz
11 = 48 kHz
3:2 Serial In Mode
00 = I
2
S
01 = Right-Justified
10 = DSP
11 = Left-Justified
1:0 Word Length
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
REV. A
AD1953
–22–
Table IV. Control Register 1 READ Definition
Register Bits Function
1 DSP Core Shutdown Complete
1 = Shutdown Complete
0 = Not Shut Down
0 Safe Memory Load Complete
1 = Complete (Note: Cleared after Read)
0 = Not Complete
Bit 0 is asserted when all requested safeload registers have been
transferred to the parameter RAM. It is cleared after the read
operation is complete.
Bit 1 is asserted after the requested shutdown of the DSP is
completed. When this bit is set, the user is free to write or read
any RAM location without causing an audio pop or click.
Table V. Control Register 2 WRITE Definition
Register Bits Function
9 Volume Ramp Speed
1 = 160 ms Full-Ramp Time
0 = 20 ms Full-Ramp Time
8 Serial Port Output Enable
1 = Enabled
0 = Disabled
7:6 Serial Port Input Select
00 = IN0
01 = IN1
10 = IN2
11 = NA
5:4 MCLK Input Select
00 = MCLK0
01 = MCLK1
10 = MCLK2
11 = NA
3 Reserved
2 MCLK In Frequency Select
0 = 512 × f
S
1 = 256 × f
S
1:0 MCLK Out Frequency Select
00 Disabled
01 512 × f
S
10 256 × f
S
11 MCLKO = MCLK_In (Feedthrough)
Control Register 2
Table V documents the contents of Control Register 2. Bits
<1:0> set the frequency of the MCLKO pin. If these bits are set
to 00, the MCLKO pin is disabled (default). When set to 01,
the MCLKO pin is set to 512 × f
S
, which is the same as the
internal master clock used by the DSP core. When set to 10,
this pin is set to 256 × f
S
, derived by dividing the internal DSP
clock by 2. In this mode, the output 256 × f
S
clock will be inverted
with respect to the input 256 × f
S
clock. This is not the case with
the feedthrough mode. When set to 11, the MCLKO pin mirrors
the selected MCLK input pin (it’s the output of the MCLK
MUX selector). Note that the internal DSP master clock may
either be the same as the selected MCLK pin (when MCLK
frequency select is set to 512 × f
S
mode) or may be derived from
the MCLK pin using internal clock doubler (when MCLK fre-
quency select is set to 256 × f
S
)
.
Bit <2> selects one of two possible MCLK input frequencies. When
set to 0 (default), the MCLK frequency is set to 512 × f
S
. In this mode,
the internal DSP clock and the external MCLK are at the same
frequency. When set to 1, the MCLK frequency is set to 256 × f
S
, and
an internal clock doubler is used to generate the DSP clock.
Bits <5:4> select one of three clock input sources using an inter-
nal MUX. To avoid click and pop noises when switching MCLK
sources, it is recommended that the user put the DSP core in
shutdown before switching MCLK sources.
Bits <7:6> select one of three serial input sources using an inter-
nal MUX. Each source selection includes a separate SDATA,
LRCLK, and BCLK input. To avoid click and pop noises when
switching serial sources, it is recommended that the user put the
DSP core in shutdown before writing to these bits.
Bit <8> is used to enable the three serial output pins. These pins
are connected to the output of the serial input MUX, which is set
by Bits <7:6>. The default is 0 (disabled).
Bit <9> changes the default setting of the volume ramp speed.
When set to 0, it will take 1024 LRCLK periods to go from full
volume (6 dB) to infinite attention. When set to 1, the same
operation will take 8192 LRCLK periods.
REV. A
AD1953
–23–
Volume Registers
The AD1953 contains eight 22-bit volume registers, one each
for the left, right, and subwoofer channels and an additional five
registers to be used by custom programs used in multichannel
applications. These registers are special because when the volume
is changed from an initial value to a new value, a linear ramp is
used to interpolate between the two values. This feature prevents
audible clicks and pops when changing volume. The ramp is
set so that it takes 512 audio frames to decrement from a volume of
1.0 (default) down to 0 (muted). The volume registers are for-
matted in 2.20 twos complement, meaning that 010000000
0000000000000 is interpreted as 1.0. Negative values can also be
written to the volume register, causing an inversion of the signal.
Negative values work as expected with the ramp feature; to go
from +1.0 to –1.0 will take 1024 LRCLKs, and the volume will
pass through 0 on the way.
Parameter RAM Contents
Table VI shows the contents of the parameter RAM. The
parameter RAM is 22 bits wide and occupies SPI addresses
0–255. The low addresses of the RAM are used to control the
biquad filters. There are 22 biquad filters in all, and each
biquad has five coefficients, resulting in a total memory usage
of 110 coefficients. There are also two tables of 33 coefficients
each that define the main and sub compressor input/output
characteristics. These are loaded with 1.0 on power-up, resulting
in no compression. Other RAM entries control other compressor
characteristics, as well as delay and spatialization settings.
The parameter RAM is initialized on power-up by an on-board
boot ROM. The default values (shown in the table) yield no
equalization, no compression, no spatialization, no delay, and
“normal” detector time constants in the compressor sections.
The functionality of the AD1953 on power-up is basically that
of a normal audio DAC with no signal-processing capability.
The data format of the Parameter RAM is twos complement
2.20 format. This means that the coefficients may range from
+2.0 (–1 LSB) to –2.0, with 1.0 represented by the binary word
0100000000000000000000.
Table VI. Parameter RAM Contents
Default Value
in Fractional
Address Function 2.20 Format
0 IIR0 Left b0 1.0
1 IIR0 Left b1 0
2 IIR0 Left b2 0
3 IIR0 Left a1 0
4 IIR0 Left a2 0
5 IIR1 Left b0 1.0
6 IIR1 Left b1 0
7 IIR1 Left b2 0
8 IIR1 Left a1 0
9 IIR1 Left a2 0
10 IIR2 Left b0 1.0
11 IIR2 Left b1 0
12 IIR2 Left b2 0
13 IIR2 Left a1 0
14 IIR2 Left a2 0
15 IIR3 Left b0 1.0
16 IIR3 Left b1 0
17 IIR3 Left b2 0
18 IIR3 Left a1 0
19 IIR3 Left a2 0
20 IIR4 Left b0 1.0
21 IIR4 Left b1 0
22 IIR4 Left b2 0
23 IIR4 Left a1 0
24 IIR4 Left a2 0
25 IIR5 Left b0 1.0
26 IIR5 Left b1 0
27 IIR5 Left b2 0
28 IIR5 Left a1 0
29 IIR5 Left a2 0
30 IIR6 Left b0 1.0
31 IIR6 Left b1 0
32 IIR6 Left b2 0
33 IIR6 Left a1 0
34 IIR6 Left a2 0
35 IIR0 Right b0 1.0
Table VI. Parameter RAM Contents (continued)
Default Value
in Fractional
Address Function 2.20 Format
36 IIR0 Right b1 0
37 IIR0 Right b2 0
38 IIR0 Right a1 0
39 IIR0 Right a2 0
40 IIR1 Right b0 1.0
41 IIR1 Right b1 0
42 IIR1 Right b2 0
43 IIR1 Right a1 0
44 IIR1 Right a2 0
45 IIR2 Right b0 1.0
46 IIR2 Right b1 0
47 IIR2 Right b2 0
48 IIR2 Right a1 0
49 IIR2 Right a2 0
50 IIR3 Right b0 1.0
51 IIR3 Right b1 0
52 IIR3 Right b2 0
53 IIR3 Right a1 0
54 IIR3 Right a2 0
55 IIR4 Right b0 1.0
56 IIR4 Right b1 0
57 IIR4 Right b2 0
58 IIR4 Right a1 0
59 IIR4 Right a2 0
60 IIR5 Right b0 1.0
61 IIR5 Right b1 0
62 IIR5 Right b2 0
63 IIR5 Right a1 0
64 IIR5 Right a2 0
65 IIR6 Right b0 1.0
66 IIR6 Right b1 0
67 IIR6 Right b2 0
68 IIR6 Right a1 0
69 IIR6 Right a2 0
70 IIR0 Xover Left b0 1.0
71 IIR0 Xover Left b1 0
REV. A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

AD1953YSTZ

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