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MAX9247ECM/V+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 7
Functional Diagram
MAX9247
TIMING AND CONTROL
DC BALANCE/
ENCODE
INPUT LATCH
RGB_IN
CNTL_IN
DE_IN
PCLK_IN
RNG0
RNG1
PWRDWN
1
0
OUT+
OUT-
PLL
PAR-TO-SER
CMF
PRE
OUT-
V
OD
V
OS
GND
R
L
/2
R
L
/2
OUT+
OUT-
OUT+
(OUT+) - (OUT-)
V
OS
(-) V
OS
(+)
((OUT+) + (OUT-))/2
V
OS
(-)
V
OD
(-)
V
OD
(-)
V
OD
= 0V
∆V
OS
= |V
OS
(+) - V
OS
(-)|
∆V
OD
= |V
OD
(+) - V
OD
(-)|
V
OD
(+)
Figure 1. LVDS DC Output Load and Parameters
MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
8 _______________________________________________________________________________________
V
ILmax
t
HIGH
t
LOW
t
T
t
R
t
F
V
IHmin
PCLK_IN
Figure 2. Parallel Clock Requirements
OUT-
C
L
C
L
R
L
OUT+
t
FALL
20%20%
(OUT+) - (OUT-)
80%
80%
t
RISE
Figure 3. Output Rise and Fall Times
V
IHmin
V
IHmin
V
IHmin
V
ILmax
V
ILmax
V
ILmax
PCLK_IN
RGB_IN[17:0]
CNTL_IN[8:0]
DE_IN
t
HOLD
t
SET
Figure 4. Synchronous Input Timing
MAX9247
27-Bit, 2.5MHz-to-42MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________ 9
t
SD
BIT 0 BIT 19
N
N + 3
EXPANDED TIME SCALE
N + 4
N
N + 1
N + 2
N - 1
RGB_IN
CNTL_IN
PCLK_IN
OUT_
Figure 5. Serializer Delay
V
OD
= 0V
HIGH IMPEDANCE
V
ILmax
t
LOCK
PWRDWN
(OUT+) - (OUT-)
PCLK_IN
Figure 6. PLL Lock Time
HIGH IMPEDANCE
V
ILmax
t
PD
PWRDWN
(OUT+) - (OUT-)
PCLK_IN
Figure 7. Power-Down Delay
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

MAX9247ECM/V+T

Mfr. #:
Buy MAX9247ECM/V+T
Manufacturer:
Maxim Integrated
Description:
Serializers & Deserializers - Serdes 27Bit 2.5-42MHz DC Blnc LVDS Serializer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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