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25C080-I/P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
25AA080/25LC080/25C080
DS21230E-page 10 1997-2012 Microchip Technology Inc.
3.5 Read Status Register (RDSR)
The Read Status Register (RDSR) instruction provides
access to the Status register. The Status register may
be read at any time, even during a write cycle. The
Status register is formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX080 is busy with a write operation. When set to a
‘
1’, a write is in progress, when set to a ‘0’, no write is
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the array, when set to a ‘
0’, the latch
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the Status
register. This bit is read only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for the RDSR timing sequence.
FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE
7 654 3 2 1 0
WPEN X X X BP1 BP0 WEL WIP
SO
SI
CS
9101112131415
1 1000000
7654 210
instruction
data from Status register
High-impedance
SCK
0 23456718
3
1997-2012 Microchip Technology Inc. DS21230E-page 11
25AA080/25LC080/25C080
3.6 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the Status reg-
ister. The array is divided up into four segments. The
user has the ability to write-protect none, one, two, or
all four of the segments of the array. The partitioning is
controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP
pin. The
Write-Protect (WP
) pin and the Write-Protect Enable
(WPEN) bit in the Status register control the program-
mable hardware write-protect feature. Hardware write
protection is enabled when WP
pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes
to nonvolatile bits in the Status register are disabled.
See Table 3-3 for a matrix of functionality on the WPEN
bit.
See Figure 3-5 for the WRSR timing sequence.
TABLE 3-2: ARRAY PROTECTION
FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE
BP1 BP0
Array Addresses
Write-Protected
00 none
01 upper 1/4
(0300h - 03FFh)
10 upper 1/2
(0200h - 03FFh)
11 all
(0000h - 03FFh)
SO
SI
CS
9101112131415
0 1000000
7654 210
instruction data to Status register
High-impedance
SCK
0 23456718
3
25AA080/25LC080/25C080
DS21230E-page 12 1997-2012 Microchip Technology Inc.
3.7 Data Protection
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
•A WRITE ENABLE instruction must be issued to
set the write enable latch
• After a byte write, page write or Status register
write, the write enable latch is reset
•CS
must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
3.8 Power-On State
The 25XX080 powers on in the following state:
• The device is in low-power Standby mode
(CS
= 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low level transition on CS
is required to
enter active state
TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX
WPEN WP WEL Protected Blocks Unprotected Blocks Status Register
XX0Protected Protected Protected
0X1Protected Writable Writable
1 Low 1 Protected Writable Protected
X High 1 Protected Writable Writable
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

25C080-I/P

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Buy 25C080-I/P
Manufacturer:
Microchip Technology
Description:
EEPROM 1kx8 - 5V
Lifecycle:
New from this manufacturer.
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