7
FN9015.3
April 18, 2005
VOUT4 can only be set from 1.7V up) by way of an external
resistor divider connected at the corresponding VSEN pin. The
new output voltage set by the external resistor divider can be
determined using the following formula:
where R
OUT
is the resistor connected from VSEN to the
output of the regulator, and R
GND
is the resistor connected
from VSEN to ground. Left open, the FIX pin is pulled high,
enabling fixed output voltage operation.
DRIVE3 (Pin 18)
Connect this pin to the gate/base of a N-type external pass
transistor (MOSFET or bipolar). This pin provides the drive
for the 1.5V regulator’s pass transistor.
VSEN3 (Pin 19)
Connect this pin to the output of the 1.5V linear regulator.
This pin is monitored for undervoltage events.
DRIVE4 (Pin 15)
Connect this pin to the base of an external bipolar transistor.
This pin provides the drive for the 1.8V regulator’s pass
transistor.
VSEN4 (Pin 14)
Connect this pin to the output of the linear 1.8V regulator.
This pin is monitored for undervoltage events.
FAULT/RT (Pin 10)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
T
) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Conversely, connecting a resistor from this pin to VCC
reduces the switching frequency according to the following
equation:
Nominally, the voltage at this pin is 1.26V. In the event of an
overvoltage or overcurrent condition, this pin is internally
pulled to VCC.
Description
Operation
The ISL6524 monitors and precisely controls 4 output voltage
levels (Refer to Figures 1, 2, 3). It is designed for
microprocessor computer applications with 3.3V, 5V, and 12V
bias input from an ATX power supply. The IC has one PWM
and three linear controllers. The PWM controller is designed to
regulate the microprocessor core voltage (V
OUT1
). The PWM
controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-
rectified buck converter configuration and regulates the core
voltage to a level programmed by the 5-bit digital-to-analog
converter (DAC). The first linear controller (EA2) is designed to
provide the AGTL+ bus voltage (V
OUT2
) by driving a MOSFET
(Q3) pass element to regulate the output voltage to a level of
1.2V. The remaining two linear controllers (EA3 and EA4)
supply the 1.5V advanced graphics port (AGP) bus power
(V
OUT3
) and the 1.8V chip set core power (V
OUT4
).
Initialization
The ISL6524 automatically initializes in ATX-based systems
upon receipt of input power. The Power-On Reset (POR)
function continually monitors the input supply voltages. The
POR monitors the bias voltage (+12V
IN
) at the VCC pin, the
5V input voltage (+5V
IN
) at the OCSET pin, and the 3.3V
input voltage (+3.3V
IN
) at the VAUX pin. The normal level on
OCSET is equal to +5V
IN
less a fixed voltage drop (see
overcurrent protection). The POR function initiates soft-start
operation after all supply voltages exceed their POR
thresholds.
Soft-Start
The 1.8V supply designed to power the chip set (OUT4),
cannot lag the ATX 3.3V by more than 2V, at any time. To
meet this special requirement, the linear block controlling
this output operates independently of the chip’s power-on
reset. Thus, DRIVE4 is driven to raise the OUT4 voltage
before the input supplies reach their POR levels. As seen in
Figure 6, at time T0 the power is turned on and the input
supplies ramp up. Immediately following, OUT4 is also
ramped up, lagging the ATX 3.3V by about 1.8V. At time T1,
the POR function initiates the SS24 soft-start sequence.
Initially, the voltage on the SS24 pin rapidly increases to
approximately 1V (this minimizes the soft-start interval).
Then, an internal 28mA current source charges an external
capacitor (C
SS24
) on the SS24 pin to about 4.5V. As the
SS24 voltage increases, the EA2 error amplifier drives Q3 to
provide a smooth transition to the final set voltage. The
OUT4 reference (clamped to SS24) increasing past the
intermediary level, established based on the ATX 3.3V
presence at the VAUX pin, brings the output in regulation
soon after T2.
As OUT2 increases past the 90% power-good level, the second
soft-start (SS13) is released. Between T2 and T3, the SS13 pin
voltage ramps from 0V to the valley of the oscillator’s triangle
wave (at 1.25V). Contingent upon OUT2 remaining above
1.08V, the first PWM pulse on PHASE1 triggers the VTTPG pin
to go high. The oscillator’s triangular wave form is compared to
the clamped error amplifier output voltage. As the SS13 pin
voltage increases, the pulse-width on the PHASE1 pin
increases, bringing the OUT1 output within regulation limits.
Similarly, the SS13 voltage clamps the reference voltage for
OUT3, enabling a controlled output voltage ramp-up. At time
T4, all output voltages are within power-good limits, situation
reported by the PGOOD pin going high.
V
OUT
1.265V 1
R
OUT
R
GND
-----------------
+
×=
Fs 200kHz
510
6
×
R
T
kΩ()
---------------------
+≈
(R
T
to GND)
Fs 200kHz
410
7
×
R
T
kΩ()
---------------------
–≈
(R
T
to 12V)
