IS31LT3360
Integrated Silicon Solution, Inc. – www.issi.com 12
Rev. C, 12/22/2013
REDUCING OUTPUT RIPPLE
A value of 1F will reduce nominal ripple current by a
factor three (approx.). Proportionally lower ripple can
be achieved with higher capacitor values. Note that
the capacitor will not affect operating frequency or
efficiency, but it will increase start-up delay, by
reducing the rate of rise of LED voltage.
OPERATION AT LOW SUPPLY VOLTAGE
The internal regulator disables the drive to the switch
until the supply has risen above the startup threshold
set internally which makes power MOSFET
on-resistance small enough. Above this threshold,
the chip will start to operate. However, with the
supply voltage below the specified minimum value,
the switch duty cycle will be high and the chip power
dissipation will be at a maximum. Care should be
taken to avoid operating the chip under such
conditions in the application, in order to minimize the
risk of exceeding the maximum allowed die
temperature. (See next section on thermal
considerations).
Note that when driving loads of two or more LEDs,
the forward drop will normally be sufficient to prevent
the chip from switching below approximately 6V. This
will minimize the risk of damage to the chip.
THERMAL CONSIDERATIONS
When operating the chip at high ambient
temperatures, or when driving maximum load current,
care must be taken to avoid exceeding the package
power dissipation limits. The maximum power
dissipation can be calculated using the following
Equation (6):
JA
AMAXJ
MAXD
TT
P
)(
)(
(6)
Where T
J(MAX)
is the maximum junction temperature,
T
A
is the ambient temperature, and
JA
is the junction
to ambient thermal resistance.
The recommended maximum operating junction
temperature, T
J(MAX)
, is 150°C and so maximum
ambient temperature is determined by the junction to
ambient thermal resistance,
JA
.
Therefore the maximum power dissipation at T
A
=
25°C is:
W
WC
CC
P
MAXD
94.0
/6.132
25150
)(
To ensure the performance, the die temperature (T
J
)
of IS31LT3360 should not exceed 125°C. The graph
below gives details for power derating.
Temperature (°C)
Power Dissipation (W)
0
0.2
0.4
0.6
0.8
1
-40 -25 -10 5 20 35 50 65 80 95 110 125
SOT89-5
Figure 19 P
D
vs. T
A
It will also increase if the efficiency of the circuit is low.
This may result from the use of unsuitable coils, or
excessive parasitic output capacitance on the switch
output.
LAYOUT CONSIDERATIONS
VIN Pin
The GND of power supply usually have some
distance to the chip GND pin, which cause parasitic
resistance and inductance. It causes ground voltage
bounce while the MOSFET is switching. Connect a
0.1µF capacitor C
2
as close to device as possible to
minimize the ground bounce.
LX Pin
The LX pin of the chip is a fast switching node, so
PCB traces should be kept as short as possible. To
minimize ground 'bounce', the ground pin of the chip
should be soldered directly to the ground plane.
Coil And Decoupling Capacitor C
1
It is particularly important to mount the coil and the
input decoupling capacitor close to the chip to
minimize parasitic resistance and inductance, which
will degrade efficiency. It is also important to take
account of any trace resistance in series with current
sense resistor R
S
.
ADJ Pin
The ADJ pin is a high impedance input, so when left
floating, PCB traces to this pin should be as short as
possible to reduce noise pickup. ADJ pin can also be
connected to a voltage between 1.2V~5V. In this
case, the internal circuit will clamp the output current
at the value which is set by V
ADJ
= 1.2V.
