AD8300ARZ-REEL

REV. A
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a
AD8300
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
OUT
GND
CLR
LD
CS
CLK
SDI
AD8300
12
12
12-BIT
DAC
REF
DAC
REGISTER
EN
SERIAL
REGISTER
+3 Volt, Serial Input
Complete 12-Bit DAC
FEATURES
Complete 12-Bit DAC
No External Components
Single +3 Volt Operation
0.5 mV/Bit with 2.0475 V Full Scale
6 s Output Voltage Settling Time
Low Power: 3.6 mW
Compact SO-8 1.5 mm Height Package
APPLICATIONS
Portable Communications
Digitally Controlled Calibration
Servo Controls
PC Peripherals
GENERAL DESCRIPTION
The AD8300 is a complete 12-bit, voltage-output digital-to-
analog converter designed to operate from a single +3 volt sup-
ply. Built using a CBCMOS process, this monolithic DAC
offers the user low cost, and ease-of-use in single-supply +3 volt
systems. Operation is guaranteed over the supply voltage range
of +2.7 V to +5.5 V making this device ideal for battery oper-
ated applications.
The 2.0475 V full-scale voltage output is laser trimmed to
maintain accuracy over the operating temperature range of the
device. The binary input data format provides an easy-to-use
one-half-millivolt-per-bit software programmability. The voltage
outputs are capable of sourcing 5 mA.
A double buffered serial data interface offers high speed, three-
wire, DSP and microcontroller compatible inputs using data in
(SDI), clock (CLK) and load strobe (LD) pins. A chip select
(CS) pin simplifies connection of multiple DAC packages by
enabling the clock input when active low. Additionally, a CLR
input sets the output to zero scale at power on or upon user
demand.
The AD8300 is specified over the extended industrial (–40°C to
+85°C) temperature range. AD8300s are available in plastic
DIP, and low profile 1.5 mm height SO-8 surface mount packages.
3.0
2.8
2.0
0.01 100.1 1.0
2.6
2.4
2.2
OUTPUT LOAD CURRENT – mA
MINIMUM SUPPLY VOLTAGE – Volts
PROPER OPERATION
WHEN V
DD
SUPPLY
VOLTAGE ABOVE
CURVE
DVFS 1 LSB
DATA = FFF
H
T
A
= +258C
Figure 1. Minimum Supply Voltage vs. Load
1.00
0.75
–1.00
0 40961024 2048
0.50
3072
0.25
0.00
–0.25
–0.50
–0.75
DIGITAL INPUT CODE – Decimal
INL LINEARITY ERROR – LSB
V
DD
= +2.7V
T
A
= –408C, +258C, +1258C
= –408C
= +258C
= +1258C
Figure 2. Linearity Error vs. Digital Code and Temperature
AD8300* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DOCUMENTATION
Data Sheet
AD8300: 3 Volt, Serial Input Complete 12-Bit DAC Data
Sheet
REFERENCE MATERIALS
Solutions Bulletins & Brochures
Digital to Analog Converters ICs Solutions Bulletin
Technical Articles
DDS Device Provides Amplitude Modulation
DESIGN RESOURCES
AD8300 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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REV. A
–2–
AD8300–SPECIFICATIONS
+3 V OPERATION
Parameter Symbol Condition Min Typ Max Units
STATIC PERFORMANCE
Resolution N [Note 1] 12 Bits
Relative Accuracy INL –2 ±1/2 +2 LSB
Differential Nonlinearity
2
DNL Monotonic –1 ±1/2 +1 LSB
Zero-Scale Error V
ZSE
Data = 000
H
+1/2 +3 mV
Full-Scale Voltage
3
V
FS
Data = FFF
H
2.039 2.0475 2.056 Volts
Full-Scale Tempco TCV
FS
[Notes 3, 4] 16 ppm/°C
ANALOG OUTPUT
Output Current (Source) I
OUT
Data = 800
H
, V
OUT
= 5 LSB 5 mA
Output Current (Sink) I
OUT
Data = 800
H
, V
OUT
= 5 LSB 2 mA
Load Regulation L
REG
R
L
= 200 to , Data = 800
H
1.5 5 LSB
Output Resistance to GND R
OUT
Data = 000
H
30
Capacitive Load C
L
No Oscillation
4
500 pF
LOGIC INPUTS
Logic Input Low Voltage V
IL
0.6 V
Logic Input High Voltage V
IH
2.1 V
Input Leakage Current I
IL
10 µA
Input Capacitance C
IL
10 pF
INTERFACE TIMING
SPECIFICATIONS
4, 5
Clock Width High t
CH
40 ns
Clock Width Low t
CL
40 ns
Load Pulsewidth t
LDW
50 ns
Data Setup t
DS
15 ns
Data Hold t
DH
15 ns
Clear Pulsewidth t
CLRW
40 ns
Load Setup t
LD1
15 ns
Load Hold t
LD2
40 ns
Select t
CSS
40 ns
Deselect t
CSH
40 ns
AC CHARACTERISTICS
4
Voltage Output Settling Time t
S
To ±0.2% of Full Scale 7 µs
To ±1 LSB of Final Value
6
14 µs
Output Slew Rate SR Data = 000
H
to FFF
H
to 000
H
2.0 V/µs
DAC Glitch 15 nV/s
Digital Feedthrough 15 nV/s
SUPPLY CHARACTERISTICS
Power Supply Range V
DD
RANGE
DNL < ±1 LSB 2.7 5.5 V
Positive Supply Current I
DD
V
DD
= 3 V, V
IL
= 0 V, Data = 000
H
1.2 1.7 mA
V
DD
= 3.6 V, V
IH
= 2.3 V, Data = FFF
H
1.9 3.0 mA
Power Dissipation P
DISS
V
DD
= 3 V, V
IL
= 0 V, Data = 000
H
3.6 5.1 mW
Power Supply Sensitivity PSS V
DD
= ±5% 0.001 0.005 %/%
NOTES
1
LSB = 0.5 mV for 0 V to +2.0475 V output range.
2
The first two codes (000
H
, 001
H
) are excluded from the linearity error measurement.
3
Includes internal voltage reference error.
4
These parameters are guaranteed by design and not subject to production testing.
5
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V.
6
The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ V
DD
= +5 V 10%, –40C T
A
+85C, unless otherwise noted)

AD8300ARZ-REEL

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Description:
Digital to Analog Converters - DAC 3V Serial Input 12B
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