REV. A
AD8300
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
+ 0.3 V
I
OUT
Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package Power Dissipation . . . . . . . . . . . . . (T
J
Max – T
A
)/θ
JA
Thermal Resistance θ
JA
8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . . 103°C/W
8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . . 158°C/W
Maximum Junction Temperature (T
J
Max) . . . . . . . . . . 150°C
Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
PIN CONFIGURATIONS
SO-8 Plastic DIP
1
2
3
4
TOP VIEW
(Not to Scale)
8
7
6
5
AD8300
V
DD
CS
CLK
SDI
V
OUT
GND
LD
CLR
1
4
8
5
ORDERING GUIDE
Package Package
Model INL Temp Description Options
AD8300AN ±2 XIND 8-Lead P-DIP N-8
AD8300AR ±2 XIND 8-Lead SOIC SO-8
NOTES
XIND = –40°C to +85°C.
The AD8300 contains 630 transistors. The die size measures 72 mil × 65 mil.
PIN DESCRIPTIONS
Pin # Name Function
1V
DD
Positive power supply input. Specified range
of operation +2.7 V to +5.5 V.
2 CS Chip Select, active low input. Disables shift
register loading when high. Does not affect
LD operation.
3 CLK Clock input, positive edge clocks data into
shift register.
4 SDI Serial Data Input, input data loads directly
into the shift register, MSB first.
5 LD Load DAC register strobes, active low.
Transfers shift register data to DAC register.
See Truth Table I for operation. Asynchro-
nous active low input.
6 CLR Resets DAC register to zero condition.
Asynchronous active low input.
7 GND Analog and Digital Ground.
8V
OUT
DAC voltage output, 2.0475 V full scale
with 0.5 mV per bit. An internal tempera-
ture stabilized reference maintains a fixed
full-scale voltage independent of time, tem-
perature and power supply variations.
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDI
t
CSS
t
LD1
t
CSH
t
LD2
CLK
CS
LD
SDI
CLK
CLR
LD
61LSB
ERROR BAND
FS
ZS
t
DS
t
DH
t
CL
t
CH
t
LDW
t
S
t
CLRW
t
S
V
OUT
Figure 3. Timing Diagram
