DEMO9S08QG8 Datasheet DEMO9S08QG8 | P7-P9

Freescale Semiconductor 7

INTRODUCTION

Before using this module, the user should be familiar with the hardware and software operation

of the target MCU. Refer to the MC9S08QG8 User Manual and MC9S08QG8 Reference

Manual for details on MCU operation. The module’s purpose is to promote the features of the

MC9S08QG8 and to assist the user in quickly developing an application in a known working

environment. Users should be familiar with memory mapping, memory types, and embedded

software design for quick, successful, application development.

The APS08QG8SLK application module is a fully assembled, fully functional module

supporting Freescale MC9S08QG8 microcontroller for educational use. The module comes

with a integrated USB Background Debug Mode (BDM), and USB cable for stand-alone

operation. Support software for this module is provided for Windows 95/98/NT/2000/XP

operating systems.

GETTING STARTED

To get started quickly, please refer to the DEMO9S08QG8 Quick Start Guide included with the

development kit. This quick start shows how to connect the board to the PC, run an LED test

program, install the correct version of CodeWarrior Development Studio, and load an Analog to

Digital (ATD) test program using CodeWarrior.

OPERATION

POWER

The APS08QG8SLK is designed to be powered from the USB_BDM during application

development. A 2.0mm barrel connector has been applied to support stand-alone operation.

In addition, the board may be powered through connector J1. The board may also be

configured to supply power through connector J1 to external circuitry.

When using the integrated USB-BDM, the board draws power from the USB bus. Total

current consumption of the board and connected circuitry, therefore, must be limited to less

than 500mA. Excessive current drain will violate the USB specification causing the USB bus

to disconnect. This will force a power-on-reset (POR).

CAUTION: Violating the USB specification will cause the USB bus to disconnect, forcing the

target to reset.

A 2.0mm barrel connector input has been provided to allow stand-alone operation. Voltage

input at this connector must be limited to between +5V and +18V. An LDO voltage regulator at

VR1 converts the input voltage to the +3.3V rail on the target board. VR1 will shut down if the

connected circuit draws excessive current. Stand-alone operation is also supported through

connector J1.

8 Freescale Semiconductor

POWER SELECT

Power may be applied to the board through the integrated USB-BDM circuitry, a 2.0mm barrel

connector, or through connector J1. Power selection is achieved by using 2 option headers:

PWR_SEL option header and the VX_EN option header.

The PWR_SEL option header selects power input either from the integrated USB-BDM

circuitry or from the on-board voltage regulator. Power input selection, from the USB-BDM or

the on-board power supply, is mutually exclusive. This prevents power-input contention from

damaging the board. The figure below details the PWR_SEL header connections.

PWR_SEL

Figure 1: PWR_SEL Option Header

PWR_SEL CONFIGURATION:

VB VDD

▪ ▪ ▪

Select power input from USB-BDM

PWR_SEL

VB VDD

▪ ▪ ▪

Select power input from VR1

Power from the integrated BDM is drawn from the USB bus and is limited to 500mA.

Excessive current drain will violate the USB specification will cause the USB bus to disconnect.

CAUTION: Violating the USB specification will cause the USB bus to disconnect. This will

cause the board to reset.

The on-board voltage regulator (VR1) accepts power input through a 2.0mm barrel connector

(PWR). Input voltage may range from +5V to +18V. The voltage regulator (VR1) provides a

+3.3V fixed output limited to 250mA. Over-temperature and over-current limits built into the

voltage regulator protects the device from excessive stresses.

The user should consider the maximum output current limit of the selected power source when

attempting to power off-board circuitry through connector J1.

VX_EN

The VX_EN option header is a 2-pin jumper that connects the target board voltage rail to J1-1.

J1-3 is connected directly to the ground plane. Use of this feature requires a regulated +3.3V

input power source. This power input is decoupled to minimize noise input but is not

regulated. Care should be exercised when using this feature; no protection is applied on this

input and damage to the target board may result if over-driven. Also, do not attempt to power

the target board through this connector while also applying power through the USB-BDM or the

PWR connector; damage to the board may result.

Freescale Semiconductor 9

Power may be sourced to off-board circuitry through the J1 connector. The current limitation of

the USB bus or the on-board regulator must be considered when attempting to source power

to external circuitry. Excessive current drain may damage the target board, the host PC USB

hub, or the on-board regulator. The figure below details the VX_EN option header

connections.

Figure 2. VX_EN Option Header

Enable power connection to connector J1

VX_EN

▪ ▪ OFF

Disable power connection to connector J1

VX_EN

CAUTION: Do not apply power to connector J1 while also sourcing power from either the PWR

connector or the USB-BDM circuit. Damage to the board may result.

NOTE: Do not exceed available current supply from the USB-BDM cable or on-board regulator

when sourcing power through connector J1 to external circuitry.

RESET SWITCH

The RESET switch provides a method to apply an asynchronous reset to the MCU and is

connected directly to the PTA5/RESET* input on the MCU. Pressing the RESET switch forces

the MCU RESET* input low. The MC9S08QG8 MCU applies an internal pull-up on the

RESET* line to prevent spurious resets and allow normal operation.

LOW VOLTAGE DETECT

The MC9S08QG8 utilizes an internal Low Voltage Detect (LVD) to protect against under-

voltage conditions. The LVD is enabled out of RESET. Consult the MC9S08QG8 Device User

Guide for details on configuring LVD operation.

STOP MODES

The MC9S08QG8 can be configured for three different low power stop modes. If stop1 or

stop2 modes are entered, an external pull-up resistor must be placed between the

PTA5/RESET*/IRQ*/TCLK pin and VDD. This pull-up resistor is not included on the

APS08QG8SLK board. If these modes will be used with this board, a 10K – 50K ohm resistor

can be placed between pins J1-1 and J1-2 to ensure proper operation of the MCU. The

jumper for the VX_EN header must also be in place in this case. Consult the MC9S08QG8

Device User Guide for more details on configuring the low power stop modes.

TIMING

By default, the APS08QG8SLK uses timing provided from an internal 32 kHz frequency

reference and an internal frequency-locked loop (FLL). The FLL output is trimmable to ± 0.2%

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

DEMO9S08QG8

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