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ADP3178JRZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
REV. A
ADP3158/ADP3178
–7–
CT Selection for Operating Frequency
The ADP3158 and ADP3178 use a constant off-time architecture
with t
OFF
determined by an external timing capacitor CT. Each
time the high-side N-channel MOSFET switch turns on, the volt-
age across CT is reset to 0 V. During the off-time, CT is charged
by a constant current of 150 µA. Once CT reaches 3.0 V, a new
on-time cycle is initiated. The value of the off-time is calculated
using the continuous-mode operating frequency. Assuming a
nominal operating frequency (f
NOM
) of 200 kHz at an output volt-
age of 1.7 V, the corresponding off-time is:
t
V
Vf
t
V
V kHz
s
OFF
OUT
IN NOM
OFF
=
×
=−
×=
1
1
1
17
5
1
200
33
–
.
. µ
(1)
The timing capacitor can be calculated from the equation:
C
tI
V
sA
V
pF
T
OFF CT
TTH
=
×
=
µ× µ
≈
()
.3 3 150
3
150
(2)
(3)
f
t
VI R R RV
VI R R RR
MIN
OFF
IN O MAX DS ON HSF SENSE L OUT
IN O MAX DS ON HSF SENSE L DS ON LSF
=×
×++
×++
1
– ()–
– ( – )
() ()
( ) () () )
The converter only operates at the nominal operating frequency
at the above-specified V
OUT
and at light load. At higher values
of V
OUT
, or under heavy load, the operating frequency decreases
due to the parasitic voltage drops across the power devices. The
actual minimum frequency at V
OUT
= 1.7 V is calculated to be
195 kHz (see Equation 3), where:
R
DS(ON)HSF
is the resistance of the high-side MOSFET
(estimated value: 14 mΩ)
R
DS(ON)LSF
is the resistance of the low-side MOSFET
(estimated value: 6 mΩ)
R
SENSE
is the resistance of the sense resistor
(estimated value: 4 mΩ)
R
L
is the resistance of the inductor
(estimated value: 3 mΩ)
Inductance Selection
The choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller-size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance means
lower ripple current and reduced conduction losses, but requires
larger-size inductors and more output capacitance for the same
peak-to-peak transient deviation. The following equation shows
the relationship between the inductance, oscillator frequency,
peak-to-peak ripple current in an inductor and input and
output voltages.
L
Vt
I
OUT OFF
L RIPPLE
=
×
()
(4)
For 4 A peak-to-peak ripple current, which corresponds to
approximately 25% of the 15 A full-load dc current in an inductor,
Equation 4 yields an inductance of
L
Vs
A
H=
×µ
=µ
17 33
4
14
..
.
A 1.5 µH inductor can be used, which gives a calculated ripple
current of 3.8 A at no load. The inductor should not saturate at
the peak current of 17 A and should be able to handle the sum
of the power dissipation caused by the average current of 15 A
in the winding and the core loss.
Designing an Inductor
Once the inductance is known, the next step is either to design an
inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. The first decision
in designing the inductor is to choose the core material. There
are several possibilities for providing low core loss at high frequen-
cies. Two examples are the powder cores (e.g., Kool-Mµ
®
from
Magnetics, Inc.) and the gapped soft ferrite cores (e.g., 3F3 or 3F4
from Philips). Low frequency powdered iron cores should be
avoided due to their high core loss, especially when the inductor
value is relatively low and the ripple current is high.
Two main core types can be used in this application. Open
magnetic loop types, such as beads, beads on leads, and rods
and slugs, provide lower cost but do not have a focused mag-
netic field in the core. The radiated EMI from the distributed
magnetic field may create problems with noise interference in
the circuitry surrounding the inductor. Closed-loop types, such
as pot cores, PQ, U, and E cores, or toroids, cost more, but
have much better EMI/RFI performance. A good compromise
between price and performance are cores with a toroidal shape.
REV. A
ADP3158/ADP3178
–8–
There are many useful references for quickly designing a power
inductor. Table II gives some examples.
Table II. Magnetics Design References
Magnetic Designer Software
Intusoft (http://www.intusoft.com)
Designing Magnetic Components for High-Frequency DC-DC
Converters
McLyman, Kg Magnetics
ISBN 1-883107-00-08
Selecting a Standard Inductor
The companies listed in Table III can provide design consul-
tation and deliver power inductors optimized for high power
applications upon request.
Table III. Power Inductor Manufacturers
Coilcraft
(847) 639-6400
http://www.coilcraft.com
Coiltronics
(561) 752-5000
http://www.coiltronics.com
Sumida Electric Company
(408) 982-9660
http://www.sumida.com
C
OUT
Selection—Determining the ESR
The required equivalent series resistance (ESR) and capacitance
drive the selection of the type and quantity of the output capaci-
tors. The ESR must be small enough to contain the voltage
deviation caused by a maximum allowable CPU transient cur-
rent within the specified voltage limits, giving consideration also
to the output ripple and the regulation tolerance. The capaci-
tance must be large enough that the voltage across the capacitor,
which is the sum of the resistive and capacitive voltage deviations,
does not deviate beyond the initial resistive deviation while the
inductor current ramps up or down to the value corresponding
to the new load current. The maximum allowed ESR also repre-
sents the maximum allowed output resistance, R
OUT
.
The cumulative errors in the output voltage regulation cuts into
the available regulation window, V
WIN
. When considering dynamic
load regulation this relates directly to the ESR. When consider-
ing dc load regulation, this relates directly to the programmed
output resistance of the power converter.
Some error sources, such as initial voltage accuracy and ripple
voltage, can be directly deducted from the available regulation
window, while other error sources scale proportionally to the
amount of voltage positioning used, which, for an optimal design,
should utilize the maximum that the regulation window will allow.
The error determination is a closed-loop calculation, but it can
be closely approximated. To maintain a conservative design while
avoiding an impractical design, various error sources should
be considered and summed statistically.
The output ripple voltage can be factored into the calculation by
summing the output ripple current with the maximum output
current to determine an effective maximum dynamic current
change. The remaining errors are summed separately according
to the formula:
VVV k
I
II
k
k
kk mV
WIN VID VID
O
OO
RCS
CSF
RT EA
=××
+
+
++
=
( – )
–
∆
∆
2
1
2
95
2
2
22
(5)
where k
VID
= 0.5% is the initial programmed voltage tolerance
from the graph of TPC 6, k
RCS
= 2% is the tolerance of the
current sense resistor, k
CSF
= 10% is the summed tolerance of
the current sense filter components, k
RT
= 2% is the tolerance of
the two termination resistors added at the COMP pin, and k
EA
= 8% accounts for the IC current loop gain tolerance including
the g
m
tolerance.
The remaining window is then divided by the maximum output
current plus the ripple to determine the maximum allowed ESR
and output resistance:
RR
V
II
mV
AA
m
E MAX OUT MAX
WIN
OO
() ()
.
==
+
=
+
=
∆
Ω
95
15 3 8
5
(6)
The output filter capacitor bank must have an ESR of less
than 5 mΩ. One can, for example, use five ZA series capacitors
from Rubycon which would give an ESR of 4.8 mΩ. Without
ADOPT voltage positioning, the ESR would need to be less than
3 mΩ, yielding a 50% increase to eight Rubycon output capacitors.
C
OUT
—Checking the Capacitance
As long as the capacitance of the output capacitor is above a
critical value and the regulating loop is compensated with ADOPT,
the actual value has no influence on the peak-to-peak deviation
of the output voltage to a full step change in the load current.
The critical capacitance can be calculated as follows:
C
I
RV
L
A
m
HmF
OUT CRIT
O
EOUT
()
.
..
=
×
×
=
Ω×
×µ=
15
517
15 26
(7)
The critical capacitance for the five ZA series Rubycon capaci-
tors is 2.6 mF while the equivalent capacitance is 5 mF. The
capacitance is safely above the critical value.
REV. A
ADP3158/ADP3178
–9–
R
SENSE
The value of R
SENSE
is based on the maximum required output
current. The current comparators of the ADP3158 and ADP3178
have a minimum current limit threshold of 69 mV. Note that the
69 mV value cannot be used for the maximum specified nominal
current, as headroom is needed for ripple current and tolerances.
The current comparator threshold sets the peak of the inductor
current yielding a maximum output current, I
O
, which equals twice
the peak inductor current value less half of the peak-to-peak induc-
tor ripple current. From this the maximum value of R
SENSE
is
calculated as:
R
V
I
I
mV
AA
m
SENSE
CS CL MIN
O
L RIPPLE
≤
+
=
+
=Ω
()( )
()
.
2
69
15 1 9
4
(8)
In this case, 4 mΩ was chosen as the closest standard value.
Once R
SENSE
has been chosen, the output current at the point
where current limit is reached, I
OUT(CL)
, can be calculated using
the maximum current sense threshold of 87 mV:
I
V
R
I
mV
m
A
A
OUT CL
CS CL MAX
SENSE
L RIPPLE
()
()( ) ( )
–
–
.
=
=
Ω
≈
2
87
4
38
2
20
(9)
At output voltages below 450 mV, the current sense threshold is
reduced to 54 mV, and the ripple current is negligible. There-
fore, at dead short the output current is reduced to:
I
mV
m
A
OUT SC()
.=
Ω
=
54
4
13 5
(10)
To safely carry the current under maximum load conditions, the
sense resistor must have a power rating of at least:
PIR AmW
R O SENSE
SENSE
=× = ×Ω=() ( ) .
22
20 4 1 6
(11)
Power MOSFETs
Two external N-channel power MOSFETs must be selected for
use with the ADP3158 and ADP3178, one for the main switch
and an identical one for the synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage (V
GS(TH)
) and the ON-resistance (R
DS(ON)
).
The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For V
IN
> 8 V,
standard threshold MOSFETs (V
GS(TH)
< 4 V) may be used. If
V
IN
is expected to drop below 8 V, logic-level threshold MOSFETs
(V
GS(TH)
< 2.5 V) are strongly recommended. Only logic-level
MOSFETs with V
GS
ratings higher than the absolute maximum
value of V
CC
should be used.
The maximum output current I
O(MAX)
determines the R
DS(ON)
requirement for the two power MOSFETs. When the ADP3158
and ADP3178 are operating in continuous mode, the simplifying
assumption can be made that one of the two MOSFETs is always
conducting the average load current. For V
IN
= 5 V and V
OUT
=
1.65 V, the maximum duty ratio of the high-side FET is:
Dft
D kHz s
HSF MAX MIN OFF
HSF MAX
()
()
–()
–(.)%
=×
=×µ=
1
1 195 3 3 36
(12)
The maximum duty ratio of the low-side (synchronous rectifier)
MOSFET is:
DD
LSF MAX HSF MAX() ()
– %==154
(13)
The maximum rms current of the high-side MOSFET is:
ID
IIII
I
AAAA
A rms
RMSHSF HSF MAX
L VALLEY L VALLEY L PEAK L PEAK
RMSHSF
=×
+×+
=×
+×+
=
()
()()()()
()
%
.(. .).
.
22
22
3
36
13 1 13 1 16 1 16 1
3
88
(14)
The maximum rms current of the low-side MOSFET is:
ID
IIII
I
AAAA
A rms
RMSLSF LSF MAX
L VALLEY L VALLEY L PEAK L PEAK
RMSLSF
=×
+×+
=×
+×+
=
()
()()()()
%
.(. .).
.
22
22
3
54
13 1 13 1 16 1 16 1
3
10 8
(15)
The R
DS(ON)
for each MOSFET can be derived from the allowable
dissipation. If 10% of the maximum output power is allowed for
MOSFET dissipation, the total dissipation will be:
PVI W
D FETs OUT OUT MAX() ( )
..=× × =01 226
(16)
Allocating half of the total dissipation for the high-side MOSFET
and half for the low-side MOSFET and assuming that switching
losses are small relative to the dc conduction losses, the required
minimum MOSFET resistances will be:
R
P
I
W
A
m
DS ON HSF
HSF
HSF
()
.
.
≤= =Ω
22
113
88
15
(17)
R
P
I
W
A
m
DS ON LSF
LSF
LSF
()
.
.
≤= =Ω
22
113
10 8
10
(18)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADP3178JRZ-REEL7

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