10
LT1680
capacitor C
SS
, the start up delay time to full available
average current will be:
t
SS
= (1.5)(10
5
)(C
SS
)
Shutdown FunctionInput Undervoltage Detect
and Threshold Hysteresis
The LT1680 RUN/SHDN pin uses a bandgap generated
reference threshold of about 1.25V. This precision thresh-
old allows use of the RUN/SHDN pin for both logic-level
shutdown applications and analog monitoring applica-
tions such as power supply sequencing.
Because an LT1680 controlled converter is a power trans-
fer device, a voltage that is lower than expected on the
input supply could require currents that exceed the sourc-
ing capabilities of that supply, causing the system to lock-
up in an undervoltage state. Input supply start-up protection
can be achieved by enabling the RUN/SHDN pin using a
resistor divider from the input supply to ground. Setting
the divider output to 1.25V when the supply is almost fully
enabled prevents the LT1680 regulator from drawing large
currents until the input supply is able to supply the
required power.
If additional hysteresis is desired for the enable function,
an external feedback resistor can be used from the LT1680
regulator output. If connection to the regulator output is
not desired, the 5V
REF
internal supply pin can be used.
Figure 3 shows an input supply sequencing configuration
on a 24V input converter. This configuration yields an
enable condition of 90% V
IN
(~21.5V) with about 10%
threshold hysteresis.
The shutdown function can be disabled by connecting the
RUN/SHDN pin to the 12V
IN
rail. This pin is internally
Figure 3. Input Supply Sequencing Programming
TIMING RESISTOR (k)
3 7 11 15 19 23 27 31 35 39 43 47
OSCILLATOR FREQUENCY (kHz)
200
180
160
140
120
100
80
60
40
1680 F02
C
CT
= 0.68nF
C
CT
= 1nF
C
CT
= 2.2nF
C
CT
= 1.5nF
Figure 2. Operating Frequency vs R
CT
, C
CT
Average Current Limit
The average current limit function is implemented using
an external capacitor (C
AVG
) connected either from the
I
AVG
pin to the V
C
pin or from the I
AVG
pin to SGND. This
capacitor forms a single-pole integrator with the 50k
output impedance of the I
AVG
pin. Precise integration
frequencies can be determined using a ground reference
integration capacitor using the relation:
f
3dB
= (3.2)(10
–6
)/C
AVG
Connecting a capacitor from the I
AVG
pin to the V
C
pin uses
an internal gain block to form an active integrator circuit,
minimizing the required capacitance for stable operation.
A typical value for this integration capacitor is 220pF from
I
AVG
to V
C
.
Shorting the I
AVG
pin to SGND will disable the average
current limit function.
Soft Start Programming
The current control pin (V
C
) limits sensed inductor current
to zero at voltages less than a transistor V
BE
, to full average
current limit at V
C
= V
BE
+ 1.8V. This generates a 1.8V full
regulation range for average load current. An internal
voltage clamp forces the V
C
pin to a V
BE
– 100mV above
the SS pin voltage. This 100mV “dead zone” assures 0%
duty cycle operation at the start of the soft start cycle or
when the soft start pin is pulled to ground. Given the
typical soft start current of 8µA and a soft start timing
V
IN
24V
16
11
160k
390k
10k
1680 F03
5V
REF
RUN/SHDN
LT1680
APPLICATIO S I FOR ATIO
WUUU
11
LT1680
clamped to 2.5V through a 20k series input resistance and
will therefore draw 0.5mA when tied directly to 12V. This
additional current can be minimized by making the con-
nection through an external resistor (100k is typically used).
Oscillator Synchronization
The LT1680 oscillator generates a modified sawtooth
waveform at the C
T
pin between low and high thresholds
of 0.8V (vl) and 2.5V (vh) respectively. The oscillator can
be synchronized by driving a TTL level pulse into the SYNC
pin. This pin connects to a one shot circuit that reduces the
oscillator high threshold to 2V for about 200ns. The SYNC
input signal should have minimum on/off times of 1µs.
The inductor core type is determined by peak current and
efficiency requirements. The inductor core must with-
stand this peak current without saturating, and the series
winding resistance and core losses should be kept as
small as is practical to maximize conversion efficiency.
The LT1680 peak current threshold is 40% greater than
the average limit threshold. Slope compensation effects
reduce this margin as duty cycle increases. This margin
must be maintained to prevent peak current limit from
corrupting the programmed value for average current
limit. Programming the peak ripple current to less than
15% of the desired average current limit value will assure
proper operation of the average current limit feature
through 90% duty cycle (see Slope Compensation).
Slope Compensation
Current mode switching regulators that operate with a
duty cycle greater than 50% and have continuous inductor
current can exhibit duty cycle instability. While a regulator
will not be damaged and may even continue to function
acceptably during this type of subharmonic oscillation, an
irritating high-pitched squeal is usually produced.
The criterion for current mode duty cycle instability is
met when the increasing slope of the inductor ripple
current is less than the decreasing slope, which is the
case at duty cycles greater than 50%. This condition is
illustrated in Figure 5a. The inductor ripple current starts
at I
1
, the beginning of each oscillator switch cycle.
Current increases at a rate S1 until the current reaches
the control trip level I
2
. The controller servo loop then
disables the switch and inductor current begins to de-
crease at a rate S2. If the current switch point (I
2
) is
perturbed slightly and increased by I, the cycle time
ends such that the minimum current point is increased by
a factor of 1 + (S2/S1) to start the next cycle. On each
successive cycle, this error is multiplied by a factor of S2/
S1. Therefore, if S2/S1 is 1, the system is unstable.
Subharmonic oscillations can be eliminated by augment-
ing the increasing ripple current slope (S1) in the control
loop. This is accomplished by adding an artificial ramp on
the inductor current waveform internal to the IC (with a
slope S
X
) as shown in Figure 5b. If the sum of the slopes
0.8V
1680 F04
2V
2.5V
(vl)
SYNC
V
CT
(vh)
FREE RUN SYNCHRONIZED
Figure 4. Free Run and Synchronized Oscillator
Waveforms (at C
T
Pin)
Inductor Selection
The inductor for an LT1680 converter is selected based on
output power, operating frequency and efficiency require-
ments. Generally, the selection of inductor value can be
reduced to desired maximum ripple current in the inductor
(I). For a boost converter, the minimum inductor value
for a given operating ripple current can be determined
using the following relation:
L
VV V
If V
MIN
IN OUT IN
O OUT
=
()
()()( )
Given an inductor value (L), the peak inductor current is
the sum of the average inductor current (I
AVG
) and half the
inductor ripple current (I), or:
II
VV V
Lf V
PK AVG
IN OUT IN
O OUT
=+
()
()()( )( )
2
APPLICATIO S I FOR ATIO
WUUU
12
LT1680
S1 + S
X
is greater than S2, this condition for subharmonic
oscillation no longer exists.
For boost topologies, the required additional current wave-
form slope, or “Slope Compensation,” follows the relation:
S
SDC
DC
X
()( )
()
12 1
1
For duty cycles less than 50% (DC < 0.5), S
X
is negative and
is not required. For duty cycles greater than 50%, S
X
takes
on values dependent on S1 and duty cycle. S1 is simply V
IN
/
L. This leads to a minimum inductance requirement for a
given V
IN
, duty cycle and slope compensation (S
X
) of:
L
V
S
DC
DC
MIN
IN
X
=
()
21
1
The LT1680 contains an internal slope compensation
ramp that has an equivalent current referred value of:
S = 0.084
f
R
X
O
SENSE
Amp/s
where f
O
is oscillator frequency and R
SENSE
is the external
current sense resistor. This yields a minimum inductance
requirement of:
L
VR DC
fDC
MIN
IN SENSE
O
()()()
()()
()
[]
21
0 084 1
.
A down side of slope compensation is that, since the IC
servo loop senses an increase in perceived inductor cur-
rent, the internal current limit functions are affected such
that the maximum current capability of a regulator is
reduced by the same amount as the effective current
referred slope compensation. The LT1680, however, uses
a current limit scheme that is independent of the slope
compensation effects (Average Current Limiting). This
provides operation at any duty cycle with no reduction in
current sourcing capability, provided ripple current peak
amplitude is less than 15% of the current limit value. For
example, if the converter is set up to average current limit
at 10A, as long as the peak inductor current is less than
11.5A, duty cycles up to 90% can be achieved without
compromising the average current limit value.
OSCILLATOR
PERIOD
TIME
0 0
5a 5b
I
T1
I
2
I
1
S1 S1S2 S2
S1 + S
X
1680 F05
Figure 5. Inductor Current at DC > 50% and
Slope Compensation Adjusted Signal
APPLICATIO S I FOR ATIO
WUUU
Figure 6. Maximum Peak Ripple Current (Normalized)
vs Duty Cycle for Average Current Limit
DUTY CYCLE
0
1.10
MAXIMUM PEAK RIPPLE CURRENT (I
PK
/I
AVG
)
1.15
1.25
1.30
1.35
0.2 0.3 0.4 0.5 0.6 0.7 0.8
1680 F06
1.20
0.1 0.9
1.40
1.45
If an inductor smaller than the minimum required for
internal slope compensation (calculated above as L
MIN
) is
desired, additional slope compensation is necessary. The
LT1680 provides this capability through the SL/ADJ pin.
This feature is implemented by referencing this pin via a
resistor divider from the 5V
REF
pin to ground. The addi-
tional slope compensation will be affected at the point in
the oscillator waveform (at pin C
T
) corresponding to the
voltage set by the resistor divider. Additional slope com-
pensation can be calculated using the relation:
S
f
RR
X
O
TH SENSE
=
()()
()( )
2500
Amp/s
where R
TH
is the Thevenin resistance of the resistor
divider. Actual compensation will actually be somewhat
greater due to internal curvature correction circuitry that

LT1680ISW#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr DC/DC Boost Cntr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union