7
LT1680
RUN/SHDN (Pin 11): Precision Referenced Shutdown.
Can be used as logic level input for shutdown control or
as an analog monitor for input supply undervoltage
protection, etc. IC is enabled when RUN/SHDN pin rising
edge exceeds 1.25V. 25mV of hysteresis helps assure
stable mode switching. All internal functions are disabled
in shutdown mode. If this function is not desired, connect
RUN/SHDN to 12V
IN
(typically through a 100k resistor).
See Applications Information.
PGND (Pin 12): Power Ground. References the output
switch and internal driver control circuits. Connect with
low impedance trace to V
IN
decoupling capacitor negative
(ground) terminal.
GATE (Pin 13): Driver Output. Connect to gate of external
power FET switch.
12V
IN
(Pin 14): 12V Power Supply Input. Bypass with at
least 1µF to PGND.
SYNC (Pin 15):
Oscillator Synchronization Pin with
TTL-Level Compatible Input. Input drives internal rising
edge triggered one shot; SYNC signal on/off times should
be 1µs (10% to 90% duty cycle at 100kHz). Does not
contain internal pull-up. Connect to SGND if not used.
5V
REF
(Pin 16): 5V Reference Output. Allows connection
of external loads up to 10mA DC. Reference is not available
during shutdown. Typically bypassed with at least 1µF
capacitor to SGND.
REFERENCE ONE SHOT
1.25V
Q
UVLO
CIRCUIT
SR
5V
REF
5V
SYNC
GATE
SENSE
+
SENSE
I
AVG
V
IN
V
OUT
R
SENSE
12V
IN
PGND
SGND
OSC
C
T
R
CT
C
CT
V
C
SL/ADJ
V
REF
V
FB
+
+
IC1
+
2.5V
1680 BD
+
EA
0.5µA
CURRENT
SENSE
AMPLIFIER
SS
1.25V
CIRCUIT
ENABLE
RUN/SHDN
+
RUN SHDN
8µA
SOFT START
12V
+
×15
V
OUT
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U
PI FU CTIO S
BLOCK DIAGRA
W
8
LT1680
Basic Control Loop
The LT1680 uses a constant frequency, current mode
architecture. The timing of the IC is provided through an
internal oscillator circuit that can be synchronized to an
external clock and is programmable to operate at frequen-
cies up to 200kHz. The oscillator creates a modified
sawtooth wave at its timing node (C
T
) with a slow charge,
rapid discharge characteristic.
During typical boost converter operation, the MOSFET
switch is enabled at the start of each oscillator cycle. The
switch stays enabled until the current through the switched
inductor, sensed via the voltage across a series sense
resistor (R
SENSE
), is sufficient to trip the current com-
parator (IC1) and reset the RS latch. When the switch is
disabled, the inductor current is redirected to the supply
output. If the current comparator threshold is not reached
throughout the entire oscillator charge period, the RS
latch is bypassed and the main switch is disabled during
the oscillator discharge time. This “minimum off time”
protects the switch, and is typically about 1µs.
The current comparator trip threshold is set on the V
C
pin,
which is the output of a transconductance amplifier, or
error amplifier (EA). The error amplifier integrates the
difference between a feedback voltage (on the V
FB
pin) and
an internal bandgap generated reference voltage of 1.25V,
forming a signal that represents required load current. If
the supplied current is insufficient for a given load, the
output will droop, thus reducing the feedback voltage. The
error amplifier responds by forcing current out of the V
C
pin, increasing the current comparator threshold. Thus,
the circuit will servo until the provided current is equal to
the required load and the average output voltage is at the
value programmed by the feedback resistors.
Input Average Current Limit
The output of the sense amplifier is monitored by a single
pole integrator comprised of an external capacitor on the
I
AVG
pin and an output impedance of approximately 50k.
If this averaged value signal exceeds a level corresponding
to 120mV across the external sense resistor, the current
comparator threshold is clamped and cannot continue to
rise in response to the error amplifier. Thus, if average
input current requirements exceed 120mV/R
SENSE
, the
supply will current limit and the output voltage will fall out
of regulation. The average current limit circuit monitors
the sense amplifier output without slope compensation or
ripple current contributions. Therefore, the average input
current limit threshold is unaffected by duty cycle.
Undervoltage Lockout
The LT1680 employs an undervoltage lockout circuit
(UVLO) that monitors the 12V
IN
supply rail. This circuit
disables the output drive capability of the LT1680 if the
12V supply drops below 9V. Unstable mode switching is
prevented through 350mV of UVLO threshold hysteresis.
Shutdown
The LT1680 can be put into low current shutdown by
pulling the RUN/SHDN pin low, disabling all circuit func-
tions. The shutdown threshold is a bandgap referred
voltage of 1.25V typical. Use of a precision threshold on
the shutdown circuit enables use of this pin for under-
voltage protection of the V
IN
supply and/or power supply
sequencing.
Soft Start
The LT1680 incorporates a soft start function that oper-
ates by slowly increasing current limit. This limit is
controlled by internally clamping the V
C
pin to a low
voltage that climbs with time as an external capacitor on
the SS pin is charged with about 8µA. This forces a
graceful climb of output current source capability, and
thus a graceful increase in output voltage until steady-
state regulation is achieved. The soft start timing capaci-
tor is clamped to ground during shutdown and during
undervoltage lockout, yielding a graceful output recovery
from either condition.
5V Internal Reference
Power for the oscillator timing elements and most other
internal LT1680 circuits is derived from an internal 5V
reference, accessible at the 5V
REF
pin. This supply pin
can be loaded with up to 10mA DC (20mA pulsed) for
convenient biasing of local elements such as control
logic, etc.
OPERATIO
U
9
LT1680
Slope Compensation
For duty cycles greater than 50%, slope compensation is
required to prevent current mode duty cycle instability in
the regulator control loop. The LT1680 employs internal
slope compensation that is adequate for most applica-
tions. However, if additional slope compensation is de-
sired, it is available through the SL/ADJ pin. Excessive
slope compensation will cause reduction in maximum
load current capability and is generally not desirable.
R
SENSE
Selection for Input Current Limit
R
SENSE
generates a voltage that is proportional to the
inductor current for use by the LT1680 current sense
amplifier. The value of R
SENSE
is based on the required
input current. The average current limit function has a
typical threshold of 120mV/R
SENSE
, or:
R
SENSE
= 120mV/I
LIMIT
Operation with V
SENSE
common mode voltage below 4.5V
may slightly degrade current limit accuracy. See Average
Current Limit Threshold Tolerance vs Common Mode
Voltage in the Typical Performance Characteristics sec-
tion for more information.
Output Voltage Programming
Output voltage is programmed through a resistor feed-
back network to the V
FB
pin (Pin 7) on the LT1680. This pin
is the inverting input of the error amplifier, which is
internally referenced to 1.25V. The divider is ratioed to
provide 1.25V at the V
FB
pin when the output is at its
desired value. Output voltage is thus set following the
relation:
V
OUT
= 1.25V(1 + R2/R1)
when an external resistor divider is connected to the
output as shown in Figure 1.
If high value feedback resistors are used, the input bias
current of the V
FB
pin (1µA maximum) could cause a slight
increase in output voltage. A Thevenin resistance at the
V
FB
pin of <5k is recommended.
Oscillator Components R
CT
and C
CT
The LT1680 oscillator creates a modified sawtooth at its
timing node (C
T
) with a slow charge, rapid discharge
characteristic. The discharge time (t
DISCH
) corresponds to
the minimum off time of the PWM controller. This limits
maximum duty cycle (DC
MAX
) to:
DC
MAX
= 1 – (t
DISCH
)(f
O
)
This relation corresponds to the minimum value of the
timing resistor (R
CT
), which can be determined according
to the following relation (R
CT
vs DC
MAX
graph appears in
the Typical Performance Characteristics section):
R
CT(MIN)
[(0.8)(10
–3
)(1 – DC
MAX
)]
–1
Values for R
CT
> 15k yield maximum duty cycles above
90%. Given a timing resistor value, the value of the timing
capacitor (C
CT
) can then be determined for desired oper-
ating frequency (f
O
) using the relation:
A plot of Operating Frequency vs R
CT
and C
CT
is shown in
Figure 2. Typical 100kHz operational values are C
CT
=
1000pF and R
CT
= 16.9k.
LT1680
V
OUT
V
FB
6
7
R1
R2
1680 F01
SGND
Figure 1. Programming LT1680 Output Voltage
OPERATIO
U
APPLICATIO S I FOR ATIO
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LT1680ISW#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Pwr DC/DC Boost Cntr
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