Philips Semiconductors Product data sheet
PCA9512Level shifting hot swappable I
2
C and SMBus buffer
2004 Oct 05
10
ELECTRICAL CHARACTERISTICS
V
CC
= 2.7 V to 5.5 V; T
amb
= –40 °C to +85 °C unless otherwise noted.
LIMITS
MIN. TYP. MAX.
Power supply
V
CC
Supply voltage Note 1. 2.7 — 5.5 V
V
CC2
Card side supply voltage Note 1. 2.7 — 5.5 V
I
VCCI
V
CC
supply current V
CC
= 5.5 V; V
SDAIN
= V
SCLIN
= 0 V — 1.2 3.6 mA
I
VCC2
V
CC
supply current V
CC
= 5.5 V; V
SDAOUT
= V
SCLOUT
= 0 V — 1.1 2.4 mA
Start-up circuitry
V
PRE
Precharge voltage SDA, SCL floating; Note 1. 0.8 1.1 1.2 V
t
EN
Enable time on power-up Note 6. — 180 — µs
t
IDLE
Bus idle time Notes 1 and 7. 50 140 250 µs
Rise time accelerators
I
PULLUPAC
Transient boosted pull-up current Positive transition on SDA, SCL,
ACC = 0.7 V × V
CC2
; V
CC
= 2.7 V;
Slew rate = 1.25 V/µs; Note 2.
1 2 — mA
V
ACCDIS
Accelerator disable threshold 0.3 × V
CC2
0.5 × V
CC2
— V
V
ACCEN
Accelerator enable threshold — 0.5 × V
CC2
0.7 × V
CC2
V
I
VACC
A
CC
input current –1 ± 0.1 1 µA
t
PDOFF
A
CC
delay, on/off — 5 — ns
Input–output connection
V
OS
Input–output offset voltage 10 kΩ to V
CC
on SDA, SCL;
V
CC
= 3.3 V, V
CC2
= 3.3 V;
V
IN
= 0.2 V; Note 1; Note 3.
0 70 150 mV
f
SCL_SDA
operating frequency Guaranteed by design, not subject to
test
0 — 400 kHz
C
IN
Digital input capacitance Guaranteed by design,
not subject to test
— — 10 pF
V
OL
LOW-level output voltage Input = 0 V. SDA, SCL pins;
I
SINK
= 3 mA; V
CC
= 2.7 V;
V
CC2
= 2.7 V; Note 1.
0 — 0.4 V
I
LI
Input leakage current SDA, SCL pins = V
CC
= 5.5 V;
V
CC2
= 5.5 V
–1 — 5 µA
Timing characteristics
f
I2C
I
2
C operating frequency Note 4 0 — 400 kHz
t
BUF
Bus free time between stop and
start condition
Note 4 1.3 — — µs
t
HD;STA
Hold time after (repeated) start
condition
Note 4 0.6 — — µs
t
SU;STA
Repeated start condition setup
time
Note 4 0.6 — — µs
t
SU;STO
Stop condition setup time Note 4 0.6 — — µs
t
HD;DAT
Data hold time Note 4 300 — — ns
t
SU;DAT
Data setup time Note 4 100 — — ns
t
LOW
Clock LOW period Note 4 1.3 — — µs
t
HIGH
Clock HIGH period Note 4 0.6 — — µs
t
f
Clock, data fall time Notes 4 and 5
20 + 0.1 × C
B
— 300 ns
t
r
Clock, data rise time Notes 4 and 5
20 + 0.1 × C
B
— 300 ns
NOTES:
1. This specification applies over the full operating temperature range.
2. I
PULLUPAC
varies with temperature and V
CC
voltage, as shown in the Typical Performance Characteristics section.
