2M x 8 Static RAM
CY7C1069AV33
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05255 Rev. *F Revised August 3, 2006
Features
•High speed
—t
AA
= 10, 12 ns
• Low active power
— 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
and CE
2
features
• Available in Pb-free and non Pb-free 54-pin TSOP II ,
non Pb-free 60-ball fine-pitch ball grid array (FBGA)
package
Functional Description
The CY7C1069AV33 is a high-performance CMOS Static
RAM organized as 2,097,152 words by 8 bits. Writing to the
device is accomplished by enabling the chip (by taking CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW.
Reading from the device is accomplished by enabling the chip
(CE
1
LOW and CE
2
HIGH) as well as forcing the Output
Enable (OE
) LOW while forcing the Write Enable (WE) HIGH.
See the truth table at the back of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a Write operation (CE
1
LOW, CE
2
HIGH, and WE
LOW).
The CY7C1069AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
60-ball fine-pitch ball grid array (FBGA) package.
Logic Block Diagram
Top View
TSOP II
WE
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
43
42
16
15
29
30
A
5
A
6
A
7
A
8
A
0
A
1
OE
V
SS
A
17
I/O
7
A
2
CE
1
I/O
0
I/O
1
A
3
A
4
18
17
20
19
27
28
25
26
22
21
23
24
I/O
2
I/O
3
A
16
A
15
V
CC
I/O
6
NC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
9
A
10
CE
2
44
46
45
47
50
49
48
51
53
52
54
V
SS
V
CC
A
19
A
18
V
CC
V
CC
V
SS
DNU
V
SS
NC
V
CC
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
A
20
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
Data in Drivers
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
2048K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
14
A
13
A
17
A
19
A
15
A
16
A
9
A
18
CE
1
CE
2
A
10
A
11
A
12
A
20
Pin Configurations
[1, 2]
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