CY7C1069AV33
Document #: 38-05255 Rev. *F Page 4 of 9
AC Switching Characteristics Over the Operating Range
[7]
Parameter Description
–10 –12
UnitMin. Max. Min. Max.
Read Cycle
t
power
V
CC
(typical) to the First Access
[8]
11ms
t
RC
Read Cycle Time 10 12 ns
t
AA
Address to Data Valid 10 12 ns
t
OHA
Data Hold from Address Change 3 3 ns
t
ACE
CE
1
LOW/CE
2
HIGH to Data Valid 10 12 ns
t
DOE
OE LOW to Data Valid 5 6 ns
t
LZOE
OE
LOW to Low-Z
[9]
11ns
t
HZOE
OE HIGH to High-Z
[
9
]
56ns
t
LZCE
CE
1
LOW/CE
2
HIGH to Low-Z
[9]
33ns
t
HZCE
CE
1
HIGH/CE
2
LOW to High-Z
[
9]
56ns
t
PU
CE
1
LOW/CE
2
HIGH to Power-up
[10]
00ns
t
PD
CE
1
HIGH/CE
2
LOW to Power-down
[10]
10 12 ns
Write Cycle
[10, 11]
t
WC
Write Cycle Time 10 12 ns
t
SCE
CE
1
LOW/CE
2
HIGH to Write End 7 8 ns
t
AW
Address Set-up to Write End 7 8 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Set-up to Write Start 0 0 ns
t
PWE
WE Pulse Width 7 8 ns
t
SD
Data Set-up to Write End 5.5 6 ns
t
HD
Data Hold from Write End 0 0 ns
t
LZWE
WE
HIGH to Low-Z
[9]
33ns
t
HZWE
WE
LOW to High-Z
[
9
]
56ns
Data Retention Waveform
Notes:
6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise.
8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a Read/Write operation is
started.
9. t
HZOE
, t
HZSCE
, t
HZWE
and t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from
steady-state voltage.
10.These parameters are guaranteed by design and are not tested.
11. The internal Write time of the memory is defined by the overlap of
CE
1
LOW/CE
2
HIGH, and WE LOW. CE
1
and WE must be LOW along with CE
2
HIGH to initiate
a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the Write.
12.The minimum Write cycle time for Write Cycle No. 3 (WE
controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
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