IRU3004CWTR Datasheet IRU3004CW, IRU3004CWTR | P10-P12

Rev. 1.7

07/16/02

IRU3004

www.irf.com

APPLICATION INFORMATION

An example of how to calculate the components for the

application circuit is given below.

Assuming, two sets of output conditions that this regu-

lator must meet:

The regulator design will be done such that it meets the

worst case requirement of each condition.

Output Capacitor Selection

The first step is to select the output capacitor. This is

done primarily by selecting the maximum ESR value

that meets the transient voltage budget of the total DVo

specification. Assuming that the regulators DC initial

accuracy plus the output ripple is 2% of the output volt-

age, then the maximum ESR of the output capacitor is

calculated as:

The Sanyo MVGX series is a good choice to achieve

both the price and performance goals. The 6MV1500GX,

1500mF, 6.3V has an ESR of less than 36mV typical.

Selecting 6 of these capacitors in parallel has an ESR

of ≈ 6mV which achieves our low ESR goal.

Other type of Electrolytic capacitors from other manu-

facturers to consider are the Panasonic FA series or the

Nichicon PL series.

Reducing the Output Capacitors Using Voltage Level

Shifting Technique

The trace resistance or an external resistor from the output

of the switching regulator to the Slot 1 can be used to

the circuit advantage and possibly reduce the number of

output capacitors, by level shifting the DC regulation point

when transition from light load to full load and vice versa.

To accomplish this, the output of the regulator is typi-

cally set about half the DC drop that results from light

load to full load. For example, if the total resistance from

the output capacitors to the Slot 1 and back to the Gnd

pin of the device is 5mV and if the total DI, the change

from light load to full load is 14A, then the output voltage

measured at the top of the resistor divider which is also

connected to the output capacitors in this case, must

be set at half of the 70mV or 35mV higher than the DAC

voltage setting. This intentional voltage level shifting

during the load transient eases the requirement for the

output capacitor ESR at the cost of load regulation. One

can show that the new ESR requirement eases up by

half the total trace resistance. For example, if the ESR

requirement of the output capacitors without voltage level

shifting must be 7mV, then after level shifting the new

ESR will only need to be 9.5mV if the trace resistance

is 5mV (7 + 5/2=9.5). However, one must be careful that

the combined “voltage level shifting” and the transient

response is still within the maximum tolerance of the

Intel specification. To insure this, the maximum trace

resistance must be less than:

Where:

Rs = Total maximum trace resistance allowed

Vspec = Intel total voltage specification

Vo = Output voltage

DVo = Output ripple voltage

DI = load current step

For example, assuming:

Vspec = ±140mV = ±0.1V for 2V output

Vo = 2V

DVo = assume 10mV = 0.01V

DI = 14.2A

Then the Rs is calculated to be:

However, if a resistor of this value is used, the maximum

power dissipated in the trace (or if an external resistor is

being used) must also be considered. For example if

Rs=12.6mV, the power dissipated is:

This is a lot of power to be dissipated in a system. So, if

the Rs=5mV, then the power dissipated is about 1W

which is much more acceptable. If level shifting is not

implemented, then the maximum output capacitor ESR

was shown previously to be 7mV which translated to ≈ 6

of the 1500mF, 6MV1500GX type Sanyo capacitors. With

Rs=5mV, the maximum ESR becomes 9.5mV which is

equivalent to ≈ 4 caps. Another important consideration

is that if a trace is being used to implement the resistor,

the power dissipated by the trace increases the case

temperature of the output capacitors which could seri-

ously effect the life time of the output capacitors.

a) Vo=2.8V, Io=14.2A, DVo=185mV, DIo=14.2A

b) Vo=2V, Io=14.2A, DVo=140mV, DIo=14.2A

ESR [ = 7mV

100

14.2

Rs [ 2 3

(Vspec - 0.02 3 Vo - DVo)

Rs [ 2 3 = 12.6mV

(0.140 - 0.02 3 2 - 0.01)

14.2

3Rs = 14.2

312.6 = 2.54W

IRU3004

Rev. 1.7

07/16/02

www.irf.com

Output Inductor Selection

The output inductance must be selected such that un-

der low line and the maximum output voltage condition,

the inductor current slope times the output capacitor

ESR is ramping up faster than the capacitor voltage is

drooping during a load current step. However, if the in-

ductor is too small, the output ripple current and ripple

voltage become too large. One solution to bring the ripple

current down is to increase the switching frequency,

however that will be at the cost of reduced efficiency and

higher system cost. The following set of formulas are

derived to achieve the optimum performance without

many design iterations.

The maximum output inductance is calculated using the

following equation:

Where:

VIN(MIN) = Minimum input voltage

Vo = 2.8V , DI = 14.2A

Assuming that the programmed switching frequency is

set at 200KHz, an inductor is designed using the

Micrometals’ powder iron core material. The summary

of the design is outlined below:

The selected core material is Powder Iron, the selected

core is T50-52D from Micro Metal wound with 8 turns of

#16 AWG wire, resulting in 3mH inductance with ≈ 3mV

of DC resistance.

Assuming L=3mH and Fsw=200KHz (switching fre-

quency), the inductor ripple current and the output ripple

voltage is calculated using the following set of equations:

In our example for Vo=2.8V and 14.2A load, assuming

IRL3103 MOSFET for both switches with maximum on-

resistance of 19mV, we have:

Power Component Selection

Assuming IRL3103 MOSFETs as power components,

we will calculate the maximum power dissipation as fol-

lows:

For high-side switch the maximum power dissipation

happens at maximum Vo and maximum duty cycle.

For synchronous MOSFET, maximum power dissipa-

tion happens at minimum Vo and minimum duty cycle.

Heat Sink Selection

Selection of the heat sink is based on the maximum

allowable junction temperature of the MOSFETS. Since

we previously selected the maximum RDS(on) at 1258C,

then we must keep the junction below this temperature.

Selecting TO-220 package gives uJC=1.88C/W (from the

venders’ data sheet) and assuming that the selected

heat sink is black anodized, the heat-sink-to-case ther-

mal resistance is uCS=0.058C/W, the maximum heat sink

temperature is then calculated as:

1.9

200000

2.8 + 0.27

5 - 0.27 + 0.27

T = = 5ms

Vsw = Vsync = 14.2 3 0.019 = 0.27V

D ≈ = 0.61

TON = 0.61 3 5 = 3.1ms

TOFF = 5 - 3.1 = 1.9ms

DIr = (2.8 + 0.27) 3 = 1.94A

DVo = 1.94 3 0.006 = 0.011V = 11mV

Ts = TJ - PD 3 (uJC + uCS)

Ts = 125 - 3.82 3 (1.8 + 0.05) = 1188C

L = 0.006390003 = 3.7mH

4.75 - 2.8

2314.2

( )

L = ESR3C3

VIN(MIN) - Vo(MAX)

2 3 ∆I

( )

T ≡ Switching Period

D ≡ Duty Cycle

Vsw ≡ High side Mosfet ON Voltage

RDS ≡ Mosfet On Resistance

Vsync ≡ Synchronous MOSFET ON Voltage

DIr ≡ Inductor Ripple Current

DVo ≡ Output Ripple Voltage

TON = D3T

TOFF = T - TON

DVo = DIr3ESR

DIr = (Vo + Vsync)3

TOFF

D ≈

Vo + Vsync

VIN - Vsw + Vsync

T =

Fsw

Vsw = Vsync = Io3RDS

DMAX ≈ = 0.65

PDH = DMAX 3 Io

3 RDS(MAX)

PDH = 0.65 3 14.2

3 0.029 = 3.8W

RDS(MAX) = Maximum RDS(ON) of the MOSFET (1258C)

(2.8 + 0.27)

(4.75 - 0.27 + 0.27)

DMIN ≈ = 0.43

PDS = (1 - DMIN) 3 Io

3 RDS(MAX)

PDS = (1 - 0.43) 3 14.2

3 0.029 = 3.33W

(2 + 0.27)

(5.25 - 0.27 + 0.27)

Rev. 1.7

07/16/02

IRU3004

www.irf.com

With the maximum heat sink temperature calculated in

the previous step, the heat-sink-to-air thermal resistance

(uSA) is calculated as follows:

Assuming TA = 358C:

Next, a heat sink with lower uSA than the one calculated

in the previous step must be selected. One way is to

simply look at the graphs of the “Heat Sink Temp Rise

Above the Ambient” vs. the “Power Dissipation” given in

the heat sink manufacturers’ catalog and select a heat

sink that results in lower temperature rise than the one

calculated in previous step. The following heat sinks from

AAVID and Thermalloy meet this criteria.

Company Part #

Thermalloy............................6078B

AAVID..................................577002

Following the same procedure for the Schottky diode

results in a heat sink with uSA=258C/W. Although it is

possible to select a slightly smaller heat sink, for sim-

plicity, the same heat sink as the one for the high side

MOSFET is also selected for the synchronous MOSFET.

Switcher Current Limit Protection

The PWM controller uses the MOSFET RDS(ON) as the

sensing resistor to sense the MOSFET current and com-

pares to a programmed voltage which is set externally

via a resistor (Rcs) placed between the drain of the

MOSFET and the “CS+” terminal of the IC as shown in

the application circuit. For example, if the desired cur-

rent limit point is set to be 22A and from our previous

selection, the maximum MOSFET RDS(ON)=19mV, then

the current sense resistor, Rcs is calculated as:

Where:

IB = 200mA is the internal current setting of the de-

vice

Switcher Timing Capacitor Selection

The switching frequency can be programmed using an

external timing capacitor. The value of Ct can be ap-

proximated using the equation below:

Where:

Ct = Timing Capacitor

Fsw = Switching Frequency

If Fsw = 200KHz:

LDO Power MOSFET Selection

The first step in selecting the power MOSFET for the

linear regulators is to select its maximum RDS(ON) based

on the input to output Dropout voltage and the maximum

load current.

For Vo = 1.5V, VIN

= 3.3V and IL = 2A:

Note that since the MOSFETs RDS(ON) increases with

temperature, this number must be divided by ≈ 1.5, in

order to find the RDS(on) max at room temperature. The

Motorola MTP3055VL has a maximum of 0.18V RDS(ON)

at room temperature, which meets our requirement.

To select the heat sink for the LDO MOSFET the first

step is to calculate the maximum power dissipation of

the device and then follow the same procedure as for the

switcher.

Where:

PD = Power Dissipation of the Linear Regulator

IL = Linear Regulator Load Current

For the 1.5V and 2A load:

Assuming TJ(max) = 1258C then:

uSA = = = 228C/W

3.82

DT = Ts - TA = 118 - 35 = 838C

Temperature Rise Above Ambient

Vcs = ICL 3 RDS = 22 3 0.019 = 0.418V

Rcs = = = 2.1KV

0.418V

200mA

Vcs

Fsw yy

3.5 3 10

-5

Ct yy = 175pF

3.5 3 10

-5

200 3 10

PD = (VIN - Vo) 3 IL

PD = (3.3 - 1.5) 3 2 = 3.6W

Ts = TJ - PD 3 (uJC + uCS)

Ts = 125 - 3.6 3 (1.8 + 0.05) = 118°C

RDS(max) = = = 0.9V

(VIN - Vo)

(3.3 - 1.5)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

IRU3004CWTR

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IC REG CTRLR INTEL 3OUT 20SOIC

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