ISL1209IU10Z-TK Datasheet ISL1209IU10Z-TK, ISL1209IU10Z, ISL1209IU10 | P10-P12

FN6109.4

October 17, 2006

Users have the option to connect EVIN (see EVINEB bit) to

an internal pull up current source that operates at 1

µA

(always on mode). User selectable event sampling modes

are also available which will effectively reduce power

consumption with 1/4-Hz, 1-Hz and 2-Hz sample detection

rates. The EVIN input is pulsed ON/OFF when in sampling

mode for power savings advantages (See tables below).

The EVIN also has a user selectable time based hysteresis

filter (see EHYS bits) to implement switch de-bouncing

during an event detection. The EVIN signal must be high for

the duration of the selected time period. The time periods

available are 0 times delay (no time based hysteresis) to

3.9ms, 15.625ms or 31.25ms (see Table 1, 2, 3, and 4).

Real Time Clock Operation

The Real Time Clock (RTC) uses an external 32.768kHz

quartz crystal to maintain an accurate internal representation

of second, minute, hour, day of week, date, month, and year.

The RTC also has leap-year correction. The clock also

corrects for months having fewer than 31 days and has a bit

that controls 24 hour or AM/PM format. When the ISL1209

powers up after the loss of both V

and V

BAT

, the clock will

not begin incrementing until at least one byte is written to the

clock register.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the

frequency of the quartz crystal that is used as the time base

for the RTC. Since the resonant frequency of a crystal is

temperature dependent, the RTC performance will also be

dependent upon temperature. The frequency deviation of

the crystal is a function of the turnover temperature of the

crystal from the crystal’s nominal frequency. For example, a

~20ppm frequency deviation translates into an accuracy of

~1 minute per month. These parameters are available from

the crystal manufacturer. The ISL1209 provides on-chip

crystal compensation networks to adjust load capacitance to

tune oscillator frequency from -94ppm to +140ppm. For

more detailed information see the Application Section.

Single Event and Interrupt

The alarm mode is enabled via the ALME bit. Choosing

single event or interrupt alarm mode is selected via the IM

bit. Note that when the frequency output function is enabled,

the alarm function is disabled.

The standard alarm allows for alarms of time, date, day of

the week, month, and year. When a time alarm occurs in

single event mode, an IRQ

pin will be pulled low and the

alarm status bit (ALM) will be set to “1”.

The pulsed interrupt mode allows for repetitive or recurring

alarm functionality. Hence, once the alarm is set, the device

will continue to alarm for each occurring match of the alarm

and present time. Thus, it will alarm as often as every minute

(if only the nth second is set) or as infrequently as once a

year (if at least the nth month is set). During pulsed interrupt

mode, the IRQ

pin will be pulled low for 250ms and the alarm

status bit (ALM) will be set to “1”.

The ALM bit can be reset by the user or cleared

automatically using the auto reset mode (see ARST bit).

The alarm function can be enabled/disabled during battery

backup mode using the FOBATB bit. For more information

on the alarm, please see the Alarm Registers Description.

Frequency Output Mode

The ISL1209 has the option to provide a frequency output

signal using the IRQ

OUT

pin. The frequency output mode

is set by using the FO bits to select 15 possible output

frequency values from 0 to 32kHz. The frequency output can

be enabled/disabled during battery backup mode using the

FOBATB bit.

General Purpose User SRAM

The ISL1209 provides 2 bytes of user SRAM. The SRAM will

continue to operate in battery backup mode. However, it

should be noted that the I

C bus is disabled in battery

backup mode.

TABLE 1. ∆I

=3V, t

HYS

=3.9ms)

SMP

DELTA I

1/4Hz 20.5nA

1Hz 82nA

2Hz 164nA

TABLE 2. ∆I

=5.0V, t

HYS

=3.9ms)

SMP

DELTA I

1/4Hz 65.8nA

1Hz 263.3nA

2Hz 526.5nA

TABLE 3. ∆I

=3.0V, t

HYS

=15.625ms)

SMP

DELTA I

1/4Hz 82nA

1Hz 328nA

2Hz 656.3nA

TABLE 4. ∆I

=5.0V, t

HYS

=15.625ms)

SMP

DELTA I

1/4Hz 264nA

1Hz 1.05µA

2Hz 2.1µA

ISL1209

FN6109.4

October 17, 2006

C Serial Interface

The ISL1209 has an I

C serial bus interface that provides

access to the control and status registers and the user

SRAM. The I

C serial interface is compatible with other

industry I

C serial bus protocols using a bidirectional data

signal (SDA) and a clock signal (SCL).

Oscillator Compensation

The ISL1209 provides the option of timing correction due to

temperature variation of the crystal oscillator for either

manufacturing calibration or active calibration. The total

possible compensation is typically -94ppm to +140ppm. Two

compensation mechanisms that are available are as follows:

1. An analog trimming (ATR) register that can be used to

adjust individual on-chip digital capacitors for oscillator

capacitance trimming. The individual digital capacitor is

selectable from a range of 9pF to 40.5pF (based upon

32.758kHz). This translates to a calculated

compensation of approximately -34ppm to +80ppm. (See

ATR description.)

2. A digital trimming register (DTR) that can be used to

adjust the timing counter by ±60ppm. (See DTR

description.)

Also provided is the ability to adjust the crystal capacitance

when the ISL1209 switches from V

to battery backup

mode. (See Battery Mode ATR Selection for more details.)

The battery-backed registers are accessible following a

slave byte of “1101111x” and reads or writes to addresses

[00h:13h]. The defined addresses and default values are

described in the Table 1. Address 09h is not used. Reads or

writes to 09h will not affect operation of the device but should

be avoided.

The contents of the registers can be modified by performing

a byte or a page write operation directly to any register

address.

The registers are divided into 4 sections. These are:

1. Real Time Clock (7 bytes): Address 00h to 06h.

2. Control and Status (5 bytes): Address 07h to 0Bh.

3. Alarm (6 bytes): Address 0Ch to 11h.

4. User SRAM (2 bytes): Address 12h to 13h.

There are no addresses above 13h.

Write capability is allowable into the RTC registers (00h to

06h) only when the WRTC bit (bit 4 of address 07h) is set to

“1”. A multi-byte read or write operation is limited to one

section per operation. Access to another section requires a

new operation. A read or write can begin at any address

within the section.

A register can be read by performing a random read at any

address at any time. This returns the contents of that register

location. Additional registers are read by performing a

sequential read. For the RTC and Alarm registers, the read

instruction latches all clock registers into a buffer, so an

update of the clock does not change the time being read. A

sequential read will not result in the output of data from the

memory array. At the end of a read, the master supplies a

stop condition to end the operation and free the bus. After a

read, the address remains at the previous address +1 so the

user can execute a current address read and continue

reading the next register.

It is not necessary to set the WRTC bit prior to writing into

the control and status, alarm, and user SRAM registers.

ISL1209

FN6109.4

October 17, 2006

TABLE 5. REGISTER MEMORY MAP

ADDR. SECTION

REG

NAME

BIT

RANGE DEFAULT 76543210

00h

RTC

SC 0 SC22 SC21 SC20 SC13 SC12 SC11 SC10 0-59 00h

01h MN 0 MN22 MN21 MN20 MN13 MN12 MN11 MN10 0-59 00h

02h HR MIL 0 HR21 HR20 HR13 HR12 HR11 HR10 0-23 00h

03h DT 0 0 DT21 DT20 DT13 DT12 DT11 DT10 1-31 00h

04h MO 0 0 0 MO20 MO13 MO12 MO11 MO10 1-12 00h

05h YR YR23 YR22 YR21 YR20 YR13 YR12 YR11 YR10 0-99 00h

06h DW00000DW2DW1DW00-600h

07h

Control

and

Status

SR ARST XTOSCB Reserved WRTC EVT ALM BAT RTCF N/A 01h

08h INT IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0 N/A 00h

09h EV EVIENB EVBATB RTCHLT EVEN EHYS1 EHYS0 ESMP1 ESMP0 N/A 00h

0Ah ATR BMATR1 BMATR0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 N/A 00h

0Bh DTR Reserved DTR2 DTR1 DTR0 N/A 00h

0Ch

Alarm

SCA ESCA ASC22 ASC21 ASC20 ASC13 ASC12 ASC11 ASC10 00-59 00h

0Dh MNA EMNA AMN22 AMN21 AMN20 AMN13 AMN12 AMN11 AMN10 00-59 00h

0Eh HRA EHRA 0 AHR21 AHR20 AHR13 AHR12 AHR11 AHR10 0-23 00h

0Fh DTA EDTA 0 ADT21 ADT20 ADT13 ADT12 ADT11 ADT10 1-31 00h

10h MOA EMOA 0 0 AMO20 AMO13 AMO12 AMO11 AMO10 1-12 00h

11h DWAEDWA0000ADW12ADW11ADW100-600h

12h

User

USR1 USR17 USR16 USR15 USR14 USR13 USR12 USR11 USR10 N/A 00h

13h USR2 USR27 USR26 USR25 USR24 USR23 USR22 USR21 USR20 N/A 00h

ISL1209

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

ISL1209IU10Z-TK

Mfr. #:

Buy ISL1209IU10Z-TK

Manufacturer:

Renesas / Intersil

Description:

Real Time Clock I2CAL TIME CLK/CLNDR W/EVENT DETCT 10LD

Lifecycle:

New from this manufacturer.

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ISL1209IU10Z-TK

ISL1209IU10Z-TK

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